ISL9208EVAL2Z Intersil, ISL9208EVAL2Z Datasheet - Page 12

• Manufacturer Part Number: ISL9208EVAL2Z
• Description: EVAL BOARD 2 FOR ISL9208
• Manufacturer: Intersil

Specifications of ISL9208EVAL2Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Registers
NOTES:
10. These status bits are automatically cleared when the register is read. All other status bits are cleared when the condition is cleared.
12. When the automatic responses are enabled, these bits are automatically reset by hardware when an overcurrent or short circuit condition turns
11. This SLEEP bit is cleared on initial power up, by the WKUP pin going high (when WKPOL = ”1”) or by the WKUP pin going low (when
09H:FFH
8. A “1” written to a control or configuration bit causes the action to be taken. A “1” read from a status bit indicates that the condition exists.
9. “Reserved” indicates that the bit or register is reserved for future expansion. When writing to addresses 2, 3, 4, and 8: write a reserved bit with
ADDR
00H
01H
02H
03H
04H
05H
06H
07H
08H
the value “0”. Do not write to reserved registers at addresses 09H through FFH. Ignore reserved bits that are returned in a read operation.
WKPOL = ”0”), and by writing a “0” to the location with an I
off the FETs. At all other times, an I
drive output circuit (though not the actual voltage at the output pin.)
Discharge Set
Cell Balance
Write Enable
FET Control
Feature Set
REGISTER
Analog Out
Charge Set
Config/Op
Operating
Reserved
(Note 10)
Status
Status
READ/WRITE
(Write only if
(Write only if
(Write only if
Read/Write
Read/Write
Read/Write
Read/Write
DISSETEN
Read/Write
Read/Write
Read/Write
CHSETEN
Read only
Read only
FSETEN
bit set)
bit set)
bit set)
12
NA
2
C write operation controls the output to the respective FET and a read returns the current state of the FET
User Flag 1
ATMPOFF
temp scan
Reserved
Reserved
Set writes
DENOCD
automatic
DENOCC
automatic
automatic
(Note 11)
FSETEN
CB7ON
external
Turn off
Turn off
Turn off
Feature
UFLG1
SLEEP
Enable
control
control
Force
Sleep
OCD
OCC
7
Disable 3.3V
User Flag 0
reg. (device
LDMONEN
Charge Set
connection
CHSETEN
Reserved
Reserved
Overcurrent Discharge
requires
CB6ON
OCDV1
OCCV1
external
Turn on
UFLG0
Overcurrent Charge
Enable
VMON
writes
Threshold Voltage
Threshold Voltage
3.3V)
DIS3
TABLE 1. REGISTERS
6
2
C command.
ISL9208
Single AFE
DISSETEN
Reserved
Reserved
Discharge
Set writes
TMP3ON
Ext over
Temp3V
CB5ON
OCDV0
OCCV0
Turn on
Enable
temp
XOT
Cell balance FET control bits
SA
5
SCD control
circuit delay
Long Short-
User Flag 3
WKUP pin
Reserved
Reserved
DENSCD
automatic
SCLONG
DISXTSD
shutdown
CB4ON
external
Turn off
Int over
Disable
thermal
UFLG3
WKUP
Status
Temp
IOT
4
RESERVED
User Flag 2
Short Circuit Discharge
time by 32
Reserved
Reserved
shutdown
Load Fail
DISITSD
(VMON)
LDFAIL
CB3ON
SCDV1
Disable
internal
thermal
UFLG2
CTDIV
charge
Divide
Threshold Voltage
AO3
3
Analog output select bits
Force POR
time by 64
Reserved
Reserved
Reserved
discharge
CB2ON
SCDV0
DTDIV
Circuit
Divide
Short
DSC
POR
AO2
2
DISWKUP
WKUP pin
Reserved
Discharge
Reserved
Overcurrent Discharge
(Note 12)
CB1ON
Turn on
OCDT1
Charge
OCCT1
Disable
Overcurrent Charge
CFET
DOC
AO1
FET
OC
1
Time-out
Time-out
November 2, 2007
Charge OC
Reserved
Reserved
Discharge
Reserved
(Note 12)
Wake Up
Turn on
OCDT0
OCCT0
WKPOL
Polarity
DFET
COC
FN6446.1
AO0
FET
0