ISL6140/41EVAL1Z Intersil, ISL6140/41EVAL1Z Datasheet - Page 5

• Manufacturer Part Number: ISL6140/41EVAL1Z
• Description: EVAL BOARD 1 FOR ISL6140/41
• Manufacturer: Intersil

Specifications of ISL6140/41EVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

.
Absolute Maximum Ratings
Supply Voltage (V
DRAIN, PWRGD, PWRGD Voltage . . . . . . . . . . . . . . . -0.3V to 100V
UV, OV Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V
SENSE, GATE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 20V
ESD Rating
Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . -40
Temperature Range (Commercial). . . . . . . . . . . . . . . . . 0
Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . 36V to 72V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
Electrical Specifications
DC PARAMETERS
V
Supply Operating Range
Supply Current
UVLO High
UVLO Low
UVLO hysteresis
GATE PIN
GATE Pin Pull-Up Current
GATE Pin Pull-Down Current
GATE Pin Pull-Down Current
GATE Pin Pull-Down Current
External GATE Drive (V
GATE High Threshold (PWRGD/PWRGD
active)
SENSE PIN
Current Limit Trip Voltage
Hard Fault Trip Voltage
SENSE Pin Current
UV PIN
UV Pin High Threshold Voltage
UV Pin Low Threshold Voltage
UV Pin Hysteresis
1. θ
2. PWRGD is referenced to DRAIN; V
DD
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V
JA
PIN
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
PARAMETER
DD
to V
DD
EE
= 20V, 80V)
). . . . . . . . . . . . . . . . . . . . -0.3V to 100V
5
Commercial (0
V
DD
PWRGD
= +48V, V
-V
DRAIN
o
SYMBOL
EE
C to 70
∆ V
V
V
I
V
SENSE
V
UVLOH
V
V
UVLOL
I
I
I
V
V
V
UVHY
I
I
PD1
PD2
PD3
= +0V Unless Otherwise Specified. All tests are over the full temperature range; either
UVH
DD
PU
HFT
UVL
GATE
GH
DD
CL
= 0V.
o
o
C to 85
C to 70
o
ISL6141, ISL6151
C) or Industrial (-40
UV = 3V; OV = V
80V
V
V
GATE Drive on, V
GATE Drive off, UV or OV false
GATE Drive off, Over-Current Time-Out
GATE Drive off; Hard Fault (Vsense > 210mV)
(V
∆V
V
V
V
UV Low to High Transition
UV High to Low Transition
o
o
DD
DD
CL
HFTV
SENSE
GATE -
C
C
GATE
= (V
Low to High transition
High to Low transition
= (V
- V
SENSE
= 50mV
V
EE)
SENSE
GATE
TEST CONDITIONS
Thermal Information
Thermal Resistance (Typical, Note 1)
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
Maximum Storage Temperature Range . . . . . . . . . . -65
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
, 20V <=V
o
- V
C to 85
8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EE
GATE =
- V
EE
; SENSE = V
)
EE
o
DD
)
C). Typical specs are at 25
V
EE
<=80V
EE
; V
DD
=
1.240
1.105
MIN
-30
20
15
13
12
40
o
C.
1.255
1.120
TYP
16.7
14.8
13.6
350
210
-1.3
135
-50
2.4
1.9
2.5
70
70
50
-
1.270
1.145
MAX
-4.0
-60
4.5
80
19
17
15
60
o
θ
C to 150
JA
(
90
Units
o
mA
mA
mA
mA
mV
mV
mV
µA
µA
C/W)
V
V
V
V
V
V
V
V
o
o
o
C
C
C