ISL6140/41EVAL1Z Intersil, ISL6140/41EVAL1Z Datasheet - Page 18

• Manufacturer Part Number: ISL6140/41EVAL1Z
• Description: EVAL BOARD 1 FOR ISL6140/41
• Manufacturer: Intersil

Specifications of ISL6140/41EVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Applications: Layout Considerations
For the minimum application, there are only 6 resistors, 2
capacitors, one IC and one FET. A sample layout is shown in
Figure 35. It assumes the IC is 8-SOIC; the FET is in a
D2PAK (or similar SMD-220 package).
Although GND planes are common with multi-level PCBs, for
a -48V system, the -48V rails (both input and output) act
more like a GND than the top 0V rail (mainly because the IC
signals are mostly referenced to the lower rail). So if
separate planes for each voltage are not an option, consider
prioritizing the bottom rails first.
NOTES:
1. Layout scale is approximate; routing lines are just for illustration
2. Approximate size of the above layout is 1.6 x 0.6 inches; almost
3. R1 sense resistor is size 2512; all other R’s and C’s shown are
4. The RL and CL are not shown on the layout.
5. R4 uses a via to connect to GND on the bottom of the board; all
6. PWRGD signal is not used here.
purposes; they do not necessarily conform to normal PCB
design rules. High current buses are wider, shown with parallel
lines.
half of the area is just the FET (D2PAK or similar SMD-220
package).
0805; they can all potentially use smaller footprints, if desired.
other routing can be on top level. (It’s even possible to eliminate
the via, for an all top-level route).
GND
-48V IN
R6
R5
R4
18
1 PG
2 OV
3 UV
4 VEE
R4
R5
R6
GND
-48V IN
FIGURE 35. ISL6141/51 SAMPLE LAYOUT (NOT TO SCALE)
R1
U1
UV
OV
V
VDD 8
EE
G 6
D 7
S 5
R1
ISL6141, ISL6151
SENSE
ISL6141
V
C1
DD
GATE
C2
R3
R2
C1
Q1
R2
Note that with the placement shown, most of the signal lines
are short, and there should not be minimal interaction
between them.
Although decoupling capacitors across the IC supply pins
are often recommended in general, this application may not
need one, nor even tolerate one. For one thing, a decoupling
cap would add to (or be swamped out by) any other input
capacitance; it also needs to be charged up when power is
applied. But more importantly, there are no high speed (or
any) input signals to the IC that need to be conditioned. If still
desired, consider the isolation resistor R10, as shown in
Figure 34.
BOM (Bill Of Materials)
R1 = 0.02Ω (5%)
R2 = 10Ω (5%)
R3 = 18kΩ (5%)
R4 = 549kΩ (1%)
R5 = 6.49kΩ (1%)
R6 = 10kΩ (1%)
C1 = 150nF (25V)
C2 = 3.3nF (100V)
Q1 = IRF530 (100V, 17A, 0.11Ω
R3
PWRGD
C2
DRAIN
G
S
-48V OUT
GND
RL
(LOAD)
CL
)
DRAIN
-48V OUT
FET
GND