LM25061MM-2EVAL/NOPB National Semiconductor, LM25061MM-2EVAL/NOPB Datasheet - Page 4

• Manufacturer Part Number: LM25061MM-2EVAL/NOPB
• Description: EVAL BOARD FOR LM25061MM-2
• Manufacturer: National Semiconductor

Specifications of LM25061MM-2EVAL/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

www.national.com
Circuit Parameter Changes
CURRENT LIMIT
The current limit threshold is set by R10 according to the fol-
lowing equation:
If the load current increases such that the voltage across R10
reaches 50 mV, the LM25061 then modulates Q1’s gate to
limit the current to that level. This evaluation board is supplied
with a 10 mohm resistor for R10, resulting in a current limit of
5A. To change the current limit threshold replace R10 with a
resistor of the required value and power capability.
POWER LIMIT
The maximum power dissipated in Q1 during turn-on, or due
to a fault, is limited by R9 and R10 according to the following
equation:
With the components supplied on the evaluation board, P
(LIM)
high, its gate is modulated to limit its drain current so the
power dissipated in Q1 does not exceed 15W. As the drain-
to-source voltage decreases, the drain current increases,
maintaining the power dissipation constant. When the drain
current reaches the current limit threshold set by R10, the
current is then maintained constant until the output voltage
reaches its final value. The current then decreases to a value
determined by the load. See Figures 3, 9, and 10.
The initial fault timeout period is equal to:
The restart fault timeout period is equal to:
The restart time is equal to:
= 15W. During turn-on, when the voltage across Q1 is
t
FAULT(Restart)
t
FAULT(Init)
I
LIM
= 50 mV/R10
= C
= C
T
T
x 2.15 x 10
x 1.776 x 10
FIGURE 4. Fault Timeout and Restart Sequence
4
4
FET
4
Each time Q1 is subjected to the maximum power limit con-
ditions it is internally stressed for a few milliseconds. For this
reason, the power limit threshold must be set lower than the
limit indicated by the FET’s SOA chart. In this evaluation
board, the power limit threshold is set at 15W, compared to
≊
The FET manufacturer should be contacted for more infor-
mation on this subject.
INSERTION TIME
The insertion time starts when the input voltage at VIN reach-
es 2.6V, and its duration is equal to
During the insertion time, Q1 is held off regardless of the volt-
age at VIN. This delay allows ringing and transients at VIN
subside before the input voltage is applied to the load via Q1.
The insertion time on this evaluation board is
Figure 8.
Fault Detection & Restart
If the load current increases to the fault level (the current limit
threshold, 5A), an internal current source charges the timing
capacitor at the TIMER pin. When the voltage at the TIMER
pin reaches 1.72V, the fault timeout period is complete, and
the LM25061 shuts off Q1. The restart sequence then begins,
consisting of seven cycles at the TIMER pin between 1.72V
and 1V, as shown in Figure 4. When the voltage at the TIMER
pin reaches 0.3V during the eighth high-to-low ramp, Q1 is
turned on. If the fault is still present, the fault timeout period
and the restart sequence repeat.
The waveform at the TIMER pin can be monitored at the test
pad located between C8 and R9. In this evaluation board the
initial fault timeout period is 14.6 ms, the restart fault timeout
period is 12.1 ms, and the restart time is 1.8 seconds. See
Figures 11,12 and 13.
40W limit indicated in the Fairchild FDD8874 data sheet.
t
INSERTION
t
RESTART
= C
= C8 x 3.13 x 10
T
x 2.65 x 10
30091404
6
5
≊
213 ms. See