LM25061MM-2EVAL/NOPB National Semiconductor, LM25061MM-2EVAL/NOPB Datasheet - Page 2

• Manufacturer Part Number: LM25061MM-2EVAL/NOPB
• Description: EVAL BOARD FOR LM25061MM-2
• Manufacturer: National Semiconductor

Specifications of LM25061MM-2EVAL/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Theory of Operation
The LM25061 provides intelligent control of the power supply
connections of a load which is to be connected to a live power
source. The two primary functions of a hot swap circuit are in-
rush current limiting during turn-on, and monitoring of the load
current for faults during normal operation. Additional functions
include Under-Voltage Lock-Out (UVLO) to ensure voltage is
supplied to the load only when the system input voltage is
above a threshold, power limiting in the series pass FET (Q1)
during turn-on, and a Power Good logic output (PGD) to in-
dicate the circuit status.
Upon applying the input voltage to the LM25061 (e.g., SW1
is switched on), Q1 is initially held off for the insertion delay
(
side. At the end of the insertion delay, if the input voltage at
VIN is above the UVLO threshold, Q1 is turned on in a con-
trolled manner to limit the in-rush current. If the in-rush current
were not limited during turn-on, the current would be high
(very high!) as the load capacitors (C3, C4) charge up, limited
only by the surge current capability of the voltage source, C7’s
characteristics, and the wiring resistance (a few milliohms).
That very high current could damage the edge connector, PC
board traces, and possibly the load capacitors receiving the
high current. Additionally, the dV/dt at the load’s input is con-
trolled to reduce possible EMI problems.
The LM25061 limits in-rush current to a safe level using a two
step process. In the first portion of the turn-on cycle, when the
voltage differential across Q1 is highest, Q1’s power dissipa-
tion is limited to a peak of 15W by monitoring its drain current
(the voltage across R10) and its drain-to-source voltage.
Their product is maintained constant by controlling the drain
current as the drain-to-source voltage decreases (as the out-
put voltage increases). This is shown in the constant power
≊
213 ms) to allow ringing and transients at the input to sub-
FIGURE 2. Evaluation Board Schematic
2
portion of Figure 3 where the drain current is increasing to
I
old (5 Amps), it is then maintained constant as the output
voltage continues to increase. When the output voltage
reaches the input voltage (V
drain current then reduces to a value determined by the load.
Q1’s gate-to-source voltage then increases to its final value.
The circuit is now in normal operation mode.
Monitoring of the load current for faults during normal opera-
tion is accomplished using the current limit circuit described
above. If the load current increases to 5 Amps (50 mV across
R10), Q1’s gate is controlled to prevent the current from in-
creasing further. When current limiting takes effect, the fault
timer limits the duration of the fault. At the end of the fault
timeout period Q1 is shut off, denying current to the load. The
LM25061-2 then initiates a restart every 1.8 seconds. The
restart consists of turning on Q1 and monitoring the load cur-
rent to determine if the fault is still present. After the fault is
removed, the circuit powers up to normal operation at the next
restart.
In a sudden overload condition (e.g., the output is shorted to
ground), it is possible the current could increase faster than
the response time of the current limit circuit. In this case, the
circuit breaker sensor shuts off Q1’s gate rapidly when the
voltage across R10 reaches
duces to the current limit threshold, the current limit circuitry
then takes over.
The PGD logic level output is low during turn-on, and switches
high when the output voltage at OUT is above 13V. PGD
switches low when the voltage at OUT is below 12.5V. The
high level voltage at PGD can be any appropriate voltage up
to +17V, and can be higher or lower than the voltages at VIN
and OUT.
LIM
. When the drain currrent reaches the current limit thresh-
DS
≊
95 mV. When the current re-
decreases to near zero), the
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