NAU8812EVB Nuvoton Technology Corporation of America, NAU8812EVB Datasheet - Page 7

• Manufacturer Part Number: NAU8812EVB
• Description: BOARD EVAL FOR NAU8812
• Manufacturer: Nuvoton Technology Corporation of America
• Series: emPowerAudio™r

Specifications of NAU8812EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.
15.
emPowerAudio
Datasheet Revision 2.0
13.7.
13.8.
13.9.
13.10. PCM TIME SLOT CONTROL & ADCOUT IMPEDANCE OPTION CONTROL .......................................... 84
13.11. REGISTER ID (READ ONLY) .................................................................................................................... 85
13.12. Reserved .................................................................................................................................................... 86
13.13. OUTPUT Driver Control Register ............................................................................................................... 86
13.14. AUTOMATIC LEVEL CONTROL ENHANCED REGISTER ....................................................................... 87
13.15. MISC CONTROL REGISTER .................................................................................................................... 88
13.16. Output Tie-Off REGISTER ......................................................................................................................... 89
13.17. ALC PEAK-TO-PEAK READOUT REGISTER ........................................................................................... 89
13.18. ALC PEAK READOUT REGISTER ............................................................................................................ 89
13.19. AUTOMUTE CONTROL AND STATUS READ REGISTER ....................................................................... 90
13.20. Output Tie-off Direct Manual Control REGISTER ...................................................................................... 90
14.1.
14.2.
14.3.
15.1.
15.2.
15.3.
15.4.
15.5.
15.6.
13.6.1.
13.6.2.
13.6.3.
13.8.1.
13.8.2.
13.9.1.
13.9.2.
13.9.3.
13.9.4.
13.9.5.
13.9.6.
13.9.7.
13.9.8.
13.9.9.
13.10.1. PCM1 TIMESLOT CONTROL REGISTER ......................................................................................... 84
13.10.2. PCM2 TIMESLOT CONTROL REGISTER ......................................................................................... 84
13.11.1. Device revision register ....................................................................................................................... 85
13.11.2. 2-WIRE ID Register (READ ONLY) ..................................................................................................... 85
13.11.3. Additional ID (READ ONLY) ................................................................................................................ 85
13.14.1. ALC1 Enhanced Register .................................................................................................................... 87
13.14.2. ALC Enhanced 2 Register ................................................................................................................... 87
15.7.
CONTROL INTERFACE TIMING DIAGRAM .................................................................................................... 91
AUDIO INTERFACE TIMING DIAGRAM........................................................................................................... 94
NOISE GAIN CONTROL REGISTER......................................................................................................... 77
PHASE LOCK LOOP (PLL) REGISTERS .................................................................................................. 78
INPUT, OUTPUT, AND MIXERS CONTROL REGISTER .......................................................................... 79
SPI WRITE TIMING DIAGRAM .................................................................................................................. 91
SPI READ TIMING DIAGRAM ................................................................................................................... 91
2-WIRE TIMING DIAGRAM ....................................................................................................................... 93
AUDIO INTERFACE IN SLAVE MODE ...................................................................................................... 94
AUDIO INTERFACE IN MASTER MODE .................................................................................................. 94
PCM AUDIO INTERFACE IN SLAVE MODE (PCM Audo Data) ................................................................ 95
PCM AUDIO INTERFACE IN MASTER MODE (PCM Audo Data) ............................................................ 95
PCM AUDIO INTERFACE IN SLAVE MODE (PCM Time Slot Mode )....................................................... 96
PCM AUDIO INTERFACE IN MASTER MODE (PCM Time Slot Mode ) ................................................... 96
™
ALC1 REGISTER ................................................................................................................................ 74
ALC2 REGISTER ................................................................................................................................ 75
ALC3 REGISTER ................................................................................................................................ 76
PLL Control Registers ......................................................................................................................... 78
Phase Lock Loop Control (PLL) Registers .......................................................................................... 78
Attenuation Control Register ............................................................................................................... 79
Input Signal Control Register .............................................................................................................. 79
PGA Gain Control Register ................................................................................................................. 80
ADC Boost Control Registers .............................................................................................................. 81
Output Register ................................................................................................................................... 81
Speaker Mixer Control Register .......................................................................................................... 82
Speaker Gain Control Register ........................................................................................................... 82
MONO Mixer Control Register ............................................................................................................ 83
Trimming Register ............................................................................................................................... 83
System Clock (MCLK) Timing Diagram ............................................................................................... 97
Page 7 of 109
NAU8812
January 2011