NAU8812EVB Nuvoton Technology Corporation of America, NAU8812EVB Datasheet - Page 44

• Manufacturer Part Number: NAU8812EVB
• Description: BOARD EVAL FOR NAU8812
• Manufacturer: Nuvoton Technology Corporation of America
• Series: emPowerAudio™r

Specifications of NAU8812EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In summary, for any given design, choose:
IMCLK = (256) * (desired codec
sample rate)
f
f
R = f
value
N = xy
K = (2
CSB/GPIO is a multi-function pin that may be used for a variety of purposes. If not required for some other purpose,
this pin may be configured to output the clock frequency from the PLL subsystem. This is the same frequency that is
available from the PLL subsystem as the input to the Master Clock Prescaler. This frequency may be optionally
divided by an additional integer factor of 2, 3, or 4, before being output on GPIO.
In an example application, a desired sample rate for the DAC is known to be 48.000kHz. Therefore, it is also known
that the IMCLK rate will be 256fs, or 12.288MHz. Because there is a fixed divide-by-four scaler on the PLL output,
then the desired PLL oscillator output frequency will be 49.152MHz.
In this example system design, there is already an available 12.000MHz clock from the USB subystem. To reduce
system cost, this clock will also be used for audio. Therefore, to use the 12MHz clock for audio, the desired fractional
multiplier ratio would be R = 49.152/12.000 = 4.096. This value, however, does not meet the requirement that the
“xy” whole number portion of the multiplier be in the inclusive range between 6 and 12. To meet the requirement, the
Master Clock Prescaler can be set for an additional divide-by-two factor. This now makes the PLL required oscillator
frequency 98.304 MHz, and the improved multiplier value is now R = 98.304/12.000 = 8.192.
emPowerAudio
Datasheet Revision 2.0
2
1
= (4 * P * IMCLK)
= (MCLK * D)
2
24
/ f
) * (0.abcdefgh)
1
12.8.2. CSB/GPIO as PLL out (f
12.8.3. Phase Locked Loop (PLL) Design Example
= xy.abcdefgh decimal
Equations
™
IMCLK = desired Master Clock
where P is the Master Clock divider
integer value;
optimal f
where D is the PLL Prescale factor of 1, or
2, and MCLK is the frequency at the
MCLK pin
which is the fractional frequency
multiplication factor for the PLL
truncated integer portion of the R value
and limited to decimal value 6, 7, 8, 9, 10,
11, or 12
rounded to the nearest whole integer
value then converted to a binary 24-bit
value
Table 24: Registers associated with PLL
PLL
2
)
: 90MHz< f
Page 44 of 109
Description
2
<100MHz
The integer values for D and P are
chosen to keep the PLL in its
optimal operating range. It may
be best to assign initial values of 1
to both D and P, and then by
inspection, determine if they
should be a different value.
NAU8812
January 2011
Notes