ISL6267HRZ Intersil, ISL6267HRZ Datasheet - Page 21

• Manufacturer Part Number: ISL6267HRZ
• Description: IC PWM CTRLR MULTIPHASE 48TQFN
• Manufacturer: Intersil

Specifications of ISL6267HRZ

• Applications: Converter, AMD Fusion™ CPU GPU
• Voltage - Input: 4.75 V ~ 5.25 V
• Number Of Outputs: 2
• Voltage - Output: 0.0125 V ~ 1.55 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The ISL6267 will adjusts the phase pulse-width relative to the
other phases to make V
I
R
Using the same components for L1, L2 and L3 provides a good
match of R
R
for the power delivery path between each inductor and the output
voltage rail, such that R
Sometimes, it is difficult to implement symmetrical layout. For
the circuit shown in Figure 16, asymmetric layout causes
different R
imbalance. Figure 17 shows a differential sensing current
balancing circuit recommended for ISL6267. The current sensing
traces should be routed to the inductor pads so they only pick up
the inductor DCR voltage. Each ISEN pin sees the average voltage
of three sources: its own, phase inductor phase-node pad, and
the other two phases inductor output side pads. Equations 8
through 10 give the ISEN pin voltages:
The ISL6267 will make V
Equations 11 and 12:
V
V
V
V
V
L1
pcb1
pcb2
ISEN1
ISEN2
ISEN3
1p
1n
INTERNAL
= I
FIGURE 17. DIFFERENTIAL-SENSING CURRENT BALANCING
+
+
TO IC
L2
V
V
= R
and R
ISEN3
ISEN2
ISEN1
2n
2p
=
=
=
= I
+
+
pcb2
Cisen
V
V
V
C
pcb1
dcr1
C
1p
1n
1n
L3
V
V
isen
isen
pcb3
3n
3n
, when R
+
+
+
, R
= R
CIRCUIT
, R
V
V
V
=
=
PHASE3
PHASE2
. It is recommended to have symmetrical layout
2n
2p
2n
PHASE1
dcr2
pcb2
V
V
pcb3
1n
1n
+
+
+
V
V
V
and R
R
R
R
R
R
R
R
R
R
+
+
dcr1
3n
3n
3p
.
and R
isen
isen
isen
isen
isen
isen
isen
isen
isen
ISEN1
pcb1
V
V
ISEN1
2p
2n
V1p
V2p
V3p
= R
+
+
dcr3
= R
pcb3
V
V
21
= V
dcr2
3n
3p
= V
. Board layout determines R
pcb2
ISEN2
values, thus creating a current
ISEN2
= R
L1
= R
L2
L3
dcr3
= V
= V
pcb3
I
I
I
L2
L1
L3
ISEN3
and
R
ISEN3
R
R
dcr2
dcr3
.
dcr1
V
V
V
, thus to achieve
3n
2n
1n
as shown in
R
R
R
pcb2
pcb3
pcb1
(EQ. 10)
(EQ. 12)
(EQ. 11)
(EQ. 8)
(EQ. 9)
V o
ISL6267
pcb1
,
Rewriting Equation 11 gives Equation 13:
Rewriting Equation 12 gives Equation 14:
Combining Equations 13 and 14 gives:
Therefore:
Current balancing (I
R
effect.
Since the slave ripple capacitor voltages mimic the inductor
currents, the R
current balancing during steady state and dynamic operations.
Figure 18 shows the current balancing performance of the
evaluation board with load transient of 12A/51A at different rep
rates. The inductor currents follow the load current dynamic
change with the output capacitors supplying the difference. The
inductor currents can track the load current well at a low
repetition rate, but cannot keep up when the repetition rate gets
into the hundred-kHz range, where it is out of the control loop
bandwidth. The controller achieves excellent current balancing in
all cases installed.
CCM Switching Frequency
The R
VW windows size and therefore sets the switching frequency.
When the ISL6267 is in continuous conduction mode (CCM), the
switching frequency is not absolutely constant due to the nature
of the R
Modulator” on page 14, the effective switching frequency
increases during load insertion and decreases during load
release to achieve fast response. Thus, the switching frequency is
relatively constant at steady state. Variation is expected when
the power stage condition, such as input voltage, output voltage,
load, etc. changes. The variation is usually less than 15% and
does not have any significant effect on output voltage ripple
magnitude. Equation 17 gives an estimate of the frequency-
setting resistor (R
approximately 300kHz switching frequency. Lower resistance
gives higher switching frequency.
R
V
V
V
R
1p
2p
1p
dcr1
dcr1
fset
–
–
–
(
V
V
V
fset
×
= R
kΩ
1n
2n
1n
I
3
L1
™ modulator. As explained in the “Multiphase R3™
)
dcr2
resistor between the COMP and the VW pins sets the
=
=
=
=
=
V
V
V
(
2p
3p
2p
R
Period μs
= R
3
dcr2
™ modulator can naturally achieve excellent
–
–
–
dcr3
fset
V
V
V
2n
3n
2n
×
L1
(
) value. A value of 8kΩ R
I
. R
L2
=
= I
) 0.29
pcb1
V
=
L2
–
3p
R
= I
–
dcr3
, R
V
L3
) 2.65
3n
pcb2
×
) is achieved when
×
I
L3
and R
pcb3
fset
do not have any
gives
January 31, 2011
(EQ. 16)
(EQ. 13)
(EQ. 14)
(EQ. 15)
(EQ. 17)
FN7801.0