ISL62883IRTZ Intersil, ISL62883IRTZ Datasheet - Page 28

• Manufacturer Part Number: ISL62883IRTZ
• Description: IC REG PWM 3PHASE BUCK 40TQFN
• Manufacturer: Intersil

Specifications of ISL62883IRTZ

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 5 V ~ 21 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 V ~ 1.5 V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN
14
15
16
17
18
19
20
21
TABLE 5. LAYOUT CONSIDERATION (Continued)
UGATE1
PHASE1
ISUM+
BOOT1
NAME
ISUM-
IMON
VDD
VIN
Place the current sensing circuit in general
proximity of the controller.
Place C82 very close to the controller.
Place NTC thermistors R42 next to Phase-
1 inductor (L1) so it senses the inductor
temperature correctly.
Each phase of the power stage sends a
pair of VSUM+ and VSUM- signals to the
controller. Run these two signals traces in
parallel fashion with decent width
(>20mil).
IMPORTANT: Sense the inductor current by
routing the sensing circuit to the inductor
pads.
Route R63 and R71 to the Phase-1 side
pad of inductor L1. Route R88 to the
output side pad of inductor L1.
Route R65 and R72 to the Phase-2 side
pad of inductor L2. Route R90 to the
output side pad of inductor L2.
Route R67 and R73 to the Phase-3 side
pad of inductor L3. Route R92 to the
output side pad of inductor L3.
If possible. Route the traces on a different
layer from the inductor pad layer and use
vias to connect the traces to the center of
the pads. If no via is allowed on the pad,
consider routing the traces into the pads
from the inside of the inductor. The
following drawings show the two preferred
ways of routing current sensing traces.
A capacitor (C16) decouples it to GND.
Place it in close proximity of the controller.
A capacitor (C17) decouples it to GND.
Place it in close proximity of the controller.
Place the filter capacitor (C21) close to the
CPU.
Use decent wide trace (>30mil). Avoid any
sensitive analog signal trace from crossing
over or getting close.
Run these two traces in parallel fashion
with decent width (>30mil). Avoid any
sensitive analog signal trace from crossing
over or getting close. Recommend routing
PHASE1 trace to the Phase-1 high-side
MOSFET (Q2 and Q8) source pins instead
of general
Phase-1 node copper.
Current-Sensing
Vias
Inductor
LAYOUT CONSIDERATION
Traces
28
Current-Sensing
ISL62883, ISL62883B
Inductor
Traces
31~3
Other
Other
PIN
22
23
24
25
26
27
28
29
30
38
39
40
7
TABLE 5. LAYOUT CONSIDERATION (Continued)
DPRSLPVR No special consideration.
CLK_EN# No special consideration.
PHASE2
UGATE2
VID0~6
LGATE1
LGATE2
BOOT2
VR_ON
NAME
VSSP1
VSSP2
PWM3
Phase
VCCP
Node
Run these two traces in parallel fashion
with decent width (>30mil). Avoid any
sensitive analog signal trace from crossing
over or getting close. Recommend routing
VSSP1 to the Phase-1 low-side MOSFET
(Q3 and Q9) source pins instead of general
power ground plane for better
performance.
No special consideration.
A capacitor (C22) decouples it to GND.
Place it in close proximity of the controller.
Run these two traces in parallel fashion
with decent width (>30mil). Avoid any
sensitive analog signal trace from crossing
over or getting close. Recommend routing
VSSP2 to the Phase-2 low-side MOSFET
(Q5 and Q1) source pins instead of general
power ground plane for better
performance.
Run these two traces in parallel fashion
with decent width (>30mil). Avoid any
sensitive analog signal trace from crossing
over or getting close. Recommend routing
PHASE2 trace to the Phase-2 high-side
MOSFET (Q4 and Q10) source pins instead
of general Phase-2 node copper.
Use decent wide trace (>30mil). Avoid any
sensitive analog signal trace from crossing
over or getting close.
No special consideration.
No special consideration.
Minimize phase node copper area. Don’t
let the phase node copper overlap
with/getting close to other sensitive
traces. Cut the power ground plane to
avoid overlapping with phase node copper.
Minimize the loop consisting of input
capacitor, high-side MOSFETs and low-side
MOSFETs (e.g.: C27, C33, Q2, Q8, Q3 and
Q9).
LAYOUT CONSIDERATION
FN6891.3