ISL62883IRTZ Intersil, ISL62883IRTZ Datasheet - Page 26

• Manufacturer Part Number: ISL62883IRTZ
• Description: IC REG PWM 3PHASE BUCK 40TQFN
• Manufacturer: Intersil

Specifications of ISL62883IRTZ

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 5 V ~ 21 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 V ~ 1.5 V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Optional Slew Rate Compensation Circuit
For 1-Tick VID Transition
During a large VID transition, the DAC steps through the
VIDs at a controlled slew rate of 2.5µs per tick (12.5mV),
controlling output voltage V
Figure 25 shows the waveforms of 1-tick VID transition.
During 1-tick VID transition, the DAC output changes at
approximately 15mV/µs slew rate, but the DAC cannot
step through multiple VIDs to control the slew rate.
Instead, the control loop response speed determines
V
voltage slew rate. However, the controller senses the
inductor current increase during the up transition, as the
I
voltage V
Similar behavior occurs during the down transition.
To control V
one can add the R
cancels I
When V
induced I
droop_vid
FIGURE 25. OPTIONAL SLEW RATE COMPENSATION
core
I
droop
slew rate. Ideally, V
t ( )
COMP
core
droop_vid
core
droop
Idroop_vid
=
waveform shows, and will droop the output
VID<0:6>
core
C
------------------------- -
increases, the time domain expression of the
R
out
Vcore
CIRCUIT FOR1-TICK VID TRANSITION
accordingly, making V
droop
INTERNAL
Vfb
Ivid
change is expressed in Equation 43:
×
slew rate during 1-tick VID transition,
TO IC
E/A
LL
.
vid
×
-C
dV
------------------ -
FB
vid
dt
Σ
core
Idroop_vid
core
26
branch, whose current I
VDAC
core
×
Rvid Cvid
Rdroop
⎛
⎜
⎜
⎝
will follow the FB pin
Ivid
1 e
DAC
–
slew rate at 5mV/µs.
X 1
-------------------------- -
C out LL
core
t –
×
VIDs
RTN
VSS
slew rate slow.
⎞
⎟
⎟
⎠
OPTIONAL
ISL62883, ISL62883B
VSSSENSE
VID<0:6>
Vcore
(EQ. 43)
vid
where C
In the mean time, the R
domain expression is shown in Equation 44:
It is desired to let I
are:
and:
The result is expressed in Equation 47:
and:
For example: given LL = 1.9mΩ, R
C
dV
and Equation 48 gives C
It’s recommended to select the calculated R
start with the calculated C
actual board to get the best performance.
During normal transient response, the FB pin voltage is
held constant, therefore is virtual ground in small signal
sense. The R
ground and the real ground, and hence has no effect on
transient response.
Voltage Regulator Thermal Throttling
FIGURE 26. CIRCUITRY ASSOCIATED WITH THE
V
C
R
I
R
C
out
vid
NTC
fb
vid
vid
vid
vid
t ( )
/dt = 15mV/µs, Equation 47 gives R
+
= 1320µF, dV
-
×
×
=
=
dV
------------
C
=
R
R
R
C
------------------------- -
dt
out
vid
NTC
NTC
R
s
C
droop
out
fb
droop
vid
=
is the total output capacitance.
=
×
THERMAL THROTTLING FEATURE OF THE
ISL62882
vid
×
C
C
------------------------- -
LL
1.24V
dV
------------
R
out
out
-C
dt
droop
×
54uA
fb
×
------------------ -
vid
dV
------------------ -
×
core
dV
------------
vid
×
LL
LL
dt
dt
core
⎛
⎜
⎜
⎝
network is between the virtual
fb
1 e
(t) cancel I
×
/dt = 5mV/us and
–
SW2
dV
------------------ -
vid
64uA
vid
SW1
------------------------------- -
R
dt
vid
core
-C
vid
= 350pF.
1.20V
+
-
vid
t –
×
value and tweak it on the
C
vid
branch current I
droop_vid
⎞
⎟
⎟
⎠
droop
INTERNAL TO
ISL62882
= 2.37kΩ,
vid
(t). So there
vid
= 2.37kΩ
value and
VR_TT#
vid
(EQ. 48)
(EQ. 45)
(EQ. 44)
(EQ. 46)
(EQ. 47)
FN6891.3
time