PCA85132U/2DB/Q1,0 NXP Semiconductors, PCA85132U/2DB/Q1,0 Datasheet - Page 19

• Manufacturer Part Number: PCA85132U/2DB/Q1,0
• Description: IC LCD DRIVER 32 UNCASED
• Manufacturer: NXP Semiconductors

Specifications of PCA85132U/2DB/Q1,0

• Display Type: LCD
• Configuration: Multiple
• Interface: I²C
• Digits Or Characters: Any Digit Type
• Current - Supply: 60µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 95°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PCA85132_1
Product data sheet
7.12 Subaddress counter
7.13 Output bank selector
7.11 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see
arriving data byte is stored at the display RAM address indicated by the data pointer. The
filling order is shown in
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
If an I
The data pointer should be re-written prior to further RAM accesses.
The storage of display data is conditioned by the content of the subaddress counter.
Storage is allowed only when the content of the subaddress counter matches with the
hardware subaddress applied to A0 and A1. The subaddress counter value is defined by
the device-select command (see
the hardware subaddress do not match then data storage is inhibited but the data pointer
is incremented as if data storage had taken place. The subaddress counter is also
incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCA85132 occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character (such as during the 27
display data byte transmitted in 1:3 multiplex mode).
The hardware subaddress must not be changed whilst the device is being accessed on
the I
The output bank selector (see
address for transfer to the display register. The actual row selected depends on the
particular LCD drive mode in operation and on the instant in the multiplex sequence.
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•
•
•
•
•
•
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In static drive mode by eight
In 1:2 multiplex drive mode by four
In 1:3 multiplex drive mode by three
In 1:4 multiplex drive mode by two
In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, row 2, and then row 3
In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
In 1:2 multiplex mode, rows 0 and 1 are selected
In static mode, row 0 is selected
2
C-bus interface.
2
C-bus data access is terminated early then the state of the data pointer is unknown.
All information provided in this document is subject to legal disclaimers.
Figure
Rev. 01 — 6 May 2010
11.
Table
Table
14) selects one of the four rows per display RAM
13). If the content of the subaddress counter and
Table
LCD driver for low multiplex rates
8). Following this command, an
PCA85132
© NXP B.V. 2010. All rights reserved.
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