PCF2113AU/10/F4,00 NXP Semiconductors, PCF2113AU/10/F4,00 Datasheet - Page 55

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PCF2113AU/10/F4,00

Manufacturer Part Number
PCF2113AU/10/F4,00
Description
IC LCD CTRLR/DVR
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCF2113AU/10/F4,00

Display Type
LCD
Configuration
5 X 8 (Matrix)
Interface
I²C
Voltage - Supply
2.2 V ~ 4 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
Die
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Digits Or Characters
-
Current - Supply
-
Lead Free Status / Rohs Status
 Details
Other names
935264031005
NXP Semiconductors
Table 25.
[1]
[2]
Table 26.
PCF2113_FAM_4
Product data sheet
Step
23
24
25
26
Step
1
2
3
4
5
6
7
8
9
10
X = not relevant.
SDA is left at high-impedance by the microcontroller during the read acknowledge.
Instruction
RS
internal reset
wait 2 ms
0
wait 2 ms
0
wait more than 40 s
0
0
0
I
‘read data’: 8
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
X
‘read data’: 8
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
‘read data’: 8
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
I
2
2
Example of I
Initialization by instruction, 8-bit interface
C-bus byte
C-bus stop
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
X
1
1
0
0
0
0
0
X
0
0
2
SCL + master acknowledge
SCL + master acknowledge
SCL + master acknowledge
C-bus operation; 1-line display (using internal reset, assuming SA0 = V
0
0
0
0
0
X
0
0
1
1
1
1
0
X
1
1
:
:
:
:
1
:
:
1
:
:
1
:
:
:
1
0
X
0
0
X
X
X
0
1
X
0
0
Rev. 04 — 4 March 2008
X
X
X
M
0
[2]
[2]
[2]
X
0
1
[1]
X
X
X
0
0
0
0
1
X
X
X
H
0
Display
PHILIPS
PHILIPS
PHILIPS
PHILIPS
Description
starting from power-on or unknown state
function set (interface is 8 bit long). Busy Flag (BF)
cannot be checked before this instruction
function set (interface is 8 bit long). BF cannot be
checked before this instruction
function set (interface is 8 bit long). BF cannot be
checked before this instruction
BF can be checked after the following instructions;
when BF is not checked the waiting time between
instructions is the specified instruction time (see
Table
function set (interface is 8 bit long); specify the
number of display lines
display off
10)
Operation
8 SCL; content loaded into interface
during previous acknowledge cycle is
shifted out over SDA; MSB is DB7;
during master acknowledge content
of DDRAM address 01 is loaded into
the I
8 SCL; code of letter ‘H’ is read first;
during master acknowledge, code of
‘I’ is loaded into the I
no master acknowledge;
-after the content of the I
interface register is shifted out no
internal action is performed;
-no new data is loaded into the
interface register;
-data register is not updated;
-address counter is not incremented
and cursor is not shifted
2
C-bus interface
LCD controllers/drivers
PCF2113x
SS
© NXP B.V. 2008. All rights reserved.
)
[1]
2
C-bus interface
…continued
2
C-bus
55 of 65

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