PCA8576CH/Q900,157 NXP Semiconductors, PCA8576CH/Q900,157 Datasheet
PCA8576CH/Q900,157
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PCA8576CH/Q900,157 Summary of contents
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PCA8576C Universal LCD driver for low multiplex rates Rev. 1 — 22 July 2010 1. General description The PCA8576C is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) multiplexed LCD containing up to four backplanes and ...
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... NXP Semiconductors 3. Ordering information Table 1. Type number PCA8576CH/Q900/1 4. Marking Table 2. Type number PCA8576CH/Q900/1 5. Block diagram V DD LCD BIAS GENERATOR V LCD CLK TIMING BLINKER SYNC OSC OSCILLATOR POWER- RESET V SS SCL INPUT FILTERS SDA Fig 1. Block diagram of PCA8576C PCA8576C Product data sheet ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. PCA8576C Product data sheet 1 n.c. S34 2 S35 3 S36 4 5 S37 6 S38 S39 7 n. SDA 11 SCL SYNC 12 CLK OSC 16 A0 Top view. For mechanical details, see Pin configuration for LQFP64 (PCA8576CH/Q900/1) All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 6.2 Pin description Table 3. Symbol SDA SCL SYNC CLK V DD OSC SA0 LCD BP0, BP2, BP1, BP3 S0 to S39 n.c. PCA8576C Product data sheet Pin description Pin LQFP64 Type (PCA8576CH/Q900/1) 10 input/output 11 input 12 input/output 13 input/output 14 supply 15 input input 19 input 20 supply ...
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... NXP Semiconductors 7. Functional description The PCA8576C is a versatile peripheral device designed to interface between any microprocessor or microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure backplanes and segments. Fig 3. The possible display configurations of the PCA8576C depend on the number of active backplane outputs required. A selection of display configurations is shown in of these configurations can be implemented in the typical system shown in Table 4 ...
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... NXP Semiconductors V V Fig 4. The host microprocessor or microcontroller maintains the 2-line I channel with the PCA8576C. Biasing voltages for the multiplexed LCD waveforms are generated internally, removing the need for an external bias generator. The internal oscillator is selected by connecting pin OSC to V power supplies (pins V 7 ...
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... NXP Semiconductors 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of ...
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... NXP Semiconductors Using Equation ⁄ 1 bias is 2 ⁄ 1 bias is 2 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V as follows: • 1:3 multiplex ( • 1:4 multiplex ( These compare with It should be noted that V PCA8576C Product data sheet ...
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... NXP Semiconductors 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Fig 5. PCA8576C Product data sheet V LCD BP0 V SS ...
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... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCA8576C allows the use of Fig 6. PCA8576C Product data sheet ⁄ 1 bias LCD BP0 LCD LCD BP1 LCD LCD LCD Sn LCD LCD ...
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... NXP Semiconductors Fig 7. PCA8576C Product data sheet V LCD LCD BP0 LCD LCD LCD BP1 LCD LCD LCD LCD LCD LCD S n LCD LCD LCD LCD state − LCD − LCD −V LCD V LCD LCD LCD 0 V state 2 − LCD − LCD − ...
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... NXP Semiconductors 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as shown in Fig 8. PCA8576C Product data sheet Figure 8. V LCD LCD BP0 LCD LCD LCD BP1 LCD LCD LCD BP2 LCD V SS ...
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... NXP Semiconductors 7.4.4 1:4 multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in BP0 BP1 BP2 BP3 Sn Sn+1 Sn+2 Sn+3 state 1 state 2 Fig 9. PCA8576C Product data sheet Figure 9. V LCD LCD LCD V SS ...
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... NXP Semiconductors 7.5 Oscillator The internal logic and the LCD drive signals of the PCA8576C are timed by the frequency f , which equals either the built-in oscillator frequency f clk f . clk(ext) The clock frequency (f for data reception from the I rate of 100 kHz, f 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to pin V output from pin CLK is the clock signal for any cascaded PCA8576C in the system ...
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... NXP Semiconductors The lower clock frequency has the disadvantage of increasing the response time when large amounts of display data are transmitted on the I process a display data byte before the next one arrives, it holds the SCL line LOW until the first display data byte is stored. This slows down the transmission rate of the I but no data loss occurs ...
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... NXP Semiconductors The display RAM bit map backplane outputs BP0 to BP3, and the columns which correspond with the segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first, second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2, and BP3 respectively ...
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LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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... NXP Semiconductors The following applies to • In the static drive mode, the eight transmitted data bits are placed in row 0 of eight successive 4-bit RAM words. • In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into row 0 and 1 of four successive 4-bit RAM words. ...
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... NXP Semiconductors 7.14 Bank selector 7.14.1 Output bank selector The output bank selector (see address for transfer to the display register. The actual row selected depends on the LCD drive mode in operation and on the instant in the multiplex sequence. • In 1:4 multiplex mode: all RAM addresses of row 0 are selected, followed sequentially by the contents of row 1, row 2, and then row 3. • ...
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... NXP Semiconductors In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. If the entire display needs to be blinked at a frequency other than the nominal blink frequency, this can be done using the mode-set command to set and reset the display enable bit E at the required rate (see 7 ...
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... NXP Semiconductors 7.16.3 System configuration A device generating a message is a transmitter and a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. The system configuration is illustrated in Figure 14. ...
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... NXP Semiconductors Fig 15. Acknowledgement of the I 7.16.5 PCA8576C I The PCA8576C acts transmit data the acknowledge signals of the selected devices. Device selection depends on the 2 I C-bus slave address, the transferred command data and the hardware subaddress. In single device application, the hardware subaddress inputs A0, A1, and A2 are normally ...
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... NXP Semiconductors 2 The I C-bus protocol is shown in condition (S) from the I slave addresses available. All PCA8576Cs with the corresponding SA0 level acknowledge in parallel with the slave address but all PCA8576Cs with the alternative SA0 level ignore the whole I After acknowledgement, one or more command bytes follow which define the status of the addressed PCA8576Cs ...
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... NXP Semiconductors Table 8. Command Bit mode-set load-data-pointer device-select bank-select blink-select 7.18.1 Mode-set command Table 9. Bit [1] The possibility to disable the display allows implementation of blinking under external control. [2] Bit B is not applicable for the static LCD drive mode. 7.18.2 Load-data-pointer command Table 10. ...
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... NXP Semiconductors 7.18.3 Device-select command Table 11. Bit 7.18.4 Bank-select command Table 12. Bit [1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. 7.18.5 Blink-select command Table 13. Bit [1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. ...
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... NXP Semiconductors 8. Internal circuitry Fig 18. Device protection diagram PCA8576C Product data sheet Universal LCD driver for low multiplex rates V LCD V SS SDA, SCL CLK, OSC A2, SA0, SYNC V DD All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C ...
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... NXP Semiconductors 9. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (V LCD display artifacts. To avoid such artifacts, V Table 14. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter LCD DD(LCD) P tot ...
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... NXP Semiconductors 10. Static characteristics Table 15. Static characteristics Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD I supply current low-power mode supply DD(lp) current Logic V LOW-level input voltage IL V HIGH-level input voltage IH V LOW-level output voltage OL V HIGH-level output voltage ...
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... NXP Semiconductors Table 15. Static characteristics Symbol Parameter LCD outputs V voltage on pin voltage on pin resistance on pin resistance on pin S S ≤ V − for ⁄ 1 [1] V bias. LCD DD 3 [2] LCD outputs are open-circuit; inputs at V < V [3] Resets all logic when V DD POR [4] Periodically sampled, not 100 % tested. ...
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... NXP Semiconductors (μA) 40 normal mode f = 200 kHz clk 30 20 power-saving mode external clock; T LCD Fig 21 function 10.2 Typical LCD output characteristics 10 R O(max) (kΩ) 1 − ° LCD amb Fig 23 function of V O(max) PCA8576C Product data sheet mbe528 −I DD(LCD) (μ kHz ...
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... NXP Semiconductors 11. Dynamic characteristics Table 16. Dynamic characteristics Symbol Parameter Timing characteristics: driver timing waveforms (see f clock frequency clk t clock HIGH time clk(H) t clock LOW time clk(L) t SYNC propagation delay PD(SYNC_N) t SYNC LOW time SYNC_NL t driver propagation delay PD(drv) 2 Timing characteristics: I ...
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... NXP Semiconductors BP0 to BP3, and S0 to S39 Fig 25. Driver timing waveforms SDA SCL SDA Fig 26. I PCA8576C Product data sheet 1/f CLK t clk(H) CLK SYNC t PD(SYNC_N BUF LOW t HD;STA 2 C-bus timing waveforms All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 ...
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... NXP Semiconductors 12. Application information 12.1 Cascaded operation In large display configurations PCA8576Cs can be recognized on the same 2 I C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable 2 I C-bus slave address (SA0). Table 17. Cluster 1 2 Cascaded PCA8576Cs are synchronized. They can share the backplane signals from one of the devices in the cascade ...
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... NXP Semiconductors V LCD V DD MICRO- PROCESSOR/ MICRO- CONTROLLER V SS Fig 27. Cascaded PCA8576C configuration The SYNC line is provided to maintain the correct synchronization between all cascaded PCA8576Cs. This synchronization is guaranteed after the power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments ...
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... NXP Semiconductors Fig 28. Synchronization of the cascade for the various PCA8576C drive modes PCA8576C Product data sheet BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode. BP0 ...
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... NXP Semiconductors 13. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors 14. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15 ...
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... NXP Semiconductors Fig 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA8576C Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors 16. Abbreviations Table 20. Acronym AEC CDM DC HBM LCD LSB MM MOS MSB MSL PCB POR RC RAM RMS SCL SDA SMD PCA8576C Product data sheet Abbreviations Description Automotive Electronics Council Charged-Device Model Direct Current Human Body Model Inter-Integrated Circuit Integrated Circuit Liquid Crystal Display ...
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... NXP Semiconductors 17. References [1] AN10365 — Surface mount reflow soldering description [2] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [4] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [5] JESD22-A114 — ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 20. Contact information For more information, please visit: For sales office addresses, please send an email to: PCA8576C Product data sheet 19 ...
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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Power-On-Reset (POR 7.2 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 6 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7 7.4 LCD drive mode waveforms . . . . . . . . . . . . . . . 9 7 ...