NCP1251ASN65T1G ON Semiconductor, NCP1251ASN65T1G Datasheet - Page 5

• Manufacturer Part Number: NCP1251ASN65T1G
• Description: IC PWM CTLR OCP LATCH OVP 6TSOP
• Manufacturer: ON Semiconductor

Specifications of NCP1251ASN65T1G

• Output Isolation: Isolated
• Frequency Range: 61kHz ~ 71kHz
• Voltage - Input: 9.4 V ~ 28 V
• Voltage - Output: 12V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 6-TSOP (0.063", 1.60mm Width)
• Number Of Outputs: 1
• Duty Cycle (max): 84 %
• Output Current: 300 mA
• Mounting Style: SMD/SMT
• Switching Frequency: 65 KHz
• Operating Supply Voltage: 28 V
• Supply Current: 2.1 mA
• Maximum Operating Temperature: + 125 C
• Fall Time: 30 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 40 ns
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS
(For typical values T
CURRENT COMPARATOR
INTERNAL OSCILLATOR
FEEDBACK SECTION
FREQUENCY FOLDBACK
INTERNAL SLOPE COMPENSATION
PROTECTIONS
3. Guaranteed by design
4. See characterization table for linearity over negative bias voltage
5. A 1 MW resistor is connected from pin 3 to the ground for the measurement.
T
T
hysteresis
T
Symbol
V
latch−blank
latch−count
T
V
IOPPo
IOOPv
IOOPv
V
IOPPs
latch−del
V
R
Timer
f
F
V
V
T
D
fold,end
OVPdel
T
f
f
V
V
TSS
V
Skip
f
swing
I
freeze
R
R
freeze
OSC
OSC
ratio
jitter
trans
ramp
ramp
DEL
latch
OVP
LEB
max
skip
fold
fold
up
eq
Default internal voltage set point for frequency foldback trip point – 45% of V
Internal peak current setpoint freeze ([31% of V
Propagation delay from current detection to gate off−state
Leading Edge Blanking Duration
Internal soft−start duration activated upon startup, auto−recovery
Setpoint decrease for pin 3 biased to –250 mV – (Note 4)
Voltage setpoint for pin 1 biased to −250 mV – (Note 4), T
Voltage setpoint for pin 1 biased to −250 mV – (Note 4), T
Setpoint decrease for pin 3 grounded
Oscillation frequency (65 kHz version)
Oscillation frequency (100 kHz version)
Maximum duty−cycle
Frequency jittering in percentage of f
Swing frequency
Internal pull−up resistor
Equivalent ac resistor from FB to GND
Pin 2 to current setpoint division ratio
Feedback voltage below which the peak current is frozen
Frequency foldback level on the feedback pin – [45% of maximum peak current
Transition frequency below which skip−cycle occurs
End of frequency foldback feedback leve, F
Skip−cycle level voltage on the feedback pin
Hysteresis on the skip comparator – (Note 3)
Internal ramp level @ 25°C – (Note 5)
Internal ramp resistance to CS pin
Latching level input
Blanking time after drive turn off
Number of clock cycles before latch confirmation
OVP detection time constant
Internal auto−recovery fault timer duration
Latched Over voltage protection on the V
Delay before OVP on V
J
= 25°C, for min/max values T
CC
confirmation
OSC
J
Rating
= −40°C to +125°C, Max T
CC
sw
http://onsemi.com
rail
= F
limit
min
)
5
J
J
= 25°C
= −40°C to 125°C
J
= 150°C, V
limit
CC
= 12 V unless otherwise noted)
Pin
3
3
4
4
−
3
3
3
3
−
−
−
−
−
2
2
−
2
−
−
−
−
4
4
3
1
−
1
−
5
5
Min
0.51
0.50
100
2.7
61
92
76
22
24
31.3
0.55
0.55
1.05
25.5
Typ
357
250
100
300
100
240
350
300
600
4.2
1.5
2.5
65
80
±5
20
16
26
30
20
20
4
0
3
1
4
0.60
0.62
Max
150
108
3.3
71
84
30
27
Unit
kHz
kHz
kHz
mV
mV
mV
mV
mV
ms
kW
kW
kW
ms
Hz
ns
ns
ms
ns
ms
%
%
%
%
V
V
V
V
V
V
V