TEA1753LT/N1,518 NXP Semiconductors, TEA1753LT/N1,518 Datasheet - Page 10

• Manufacturer Part Number: TEA1753LT/N1,518
• Description: IC CTLR SMPS SW MODE 16SO
• Manufacturer: NXP Semiconductors

Specifications of TEA1753LT/N1,518

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
TEA1753LT
Product data sheet
7.2.2 Valley switching and demagnetization (PFCAUX pin)
7.2.3 Frequency limitation
7.2.4 Mains voltage compensation (VINSENSE pin)
7.2.5 Soft start-up (pin PFCSENSE)
The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry
connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the
voltage across the PFC MOSFET. The next stroke is started if the voltage across the PFC
MOSFET is at its minimum in order to reduce switching losses and
ElectroMagnetic Interference (EMI) (valley switching).
If no demagnetization signal is detected on the PFCAUX pin, the controller generates a
Zero Current Signal (ZCS), 50 μs after the last PFCGATE signal.
If no valley signal is detected on the PFCAUX pin, the controller generates a valley signal
4 μs after demagnetization is detected.
To protect the internal circuitry during lightning events, for example, it is advisable to add a
5 kΩ series resistor to this pin. To prevent incorrect switching due to external disturbance,
the resistor should be placed close to the IC on the printed-circuit board.
To optimize the transformer and minimize switching losses, the switching frequency is
limited to f
limit, the system switches over to discontinuous conduction mode. Also here, the PFC
MOSFET is only switched on at a minimum voltage across the switch (valley switching).
The mathematical equation for the transfer function of a power factor corrector contains
the square of the mains input voltage. In a typical application this results in a low
bandwidth for low mains input voltages, while at high mains input voltages the Mains
Harmonic Reduction (MHR) requirements may be hard to meet.
To compensate for the mains input voltage influence, TEA1753LT contains a correction
circuit. Via the VINSENSE pin the average input voltage is measured and the information
is fed to an internal compensation circuit. With this compensation it is possible to keep the
regulation loop bandwidth constant over the full mains input range, yielding a fast transient
response on load steps, while still complying with class-D MHR requirements.
In a typical application, the bandwidth of the regulation loop is set by a resistor and two
capacitors on the PFCCOMP pin.
To prevent audible transformer noise at start-up or during hiccup, the transformer peak
current is increased slowly by the soft start function. This can be achieved by inserting
R
current source charges the capacitor to:
The voltage is limited to V
The start level and the time constant of the increasing primary current level can be
adjusted externally by changing the values of R
V
τsoftstart
SS1
PFCSENSE
and C
sw(PFC)max
=
SS1
=
3
I
start soft
×
between pin PFCSENSE and current sense resistor R
All information provided in this document is subject to legal disclaimers.
R
SS1
(
. If the frequency for quasi-resonant operation is above the f
×
)PFC
C
Rev. 2 — 8 April 2011
SS1
start(soft)PFC
×
R
SS1
.
SS1
and C
GreenChip III SMPS control IC
SS1
.
TEA1753LT
SENSE1
© NXP B.V. 2011. All rights reserved.
. An internal
sw(PFC)max
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