CY7C1520KV18-200BZC Cypress Semiconductor Corp, CY7C1520KV18-200BZC Datasheet

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... CY7C1518KV18 and two 36-bit words in the case of CY7C1520KV18 sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same ...

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... Logic Block Diagram (CY7C1527KV18 (21:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [0] Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Write Write Reg Reg Output Logic Control Read Data Reg Reg. Reg. 8 Reg. Write Write Reg Reg Output Logic Control Read Data Reg ...

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... Logic Block Diagram (CY7C1518KV18) Burst A0 Logic (21:0) A Address (21:1) Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [1:0] Logic Block Diagram (CY7C1520KV18) Burst A0 Logic (20:0) A Address (20:1) Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [3:0] Document Number: 001-00437 Rev. *J ...

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... Depth Expansion ......................................................... 9 Programmable Impedance ........................................ 10 Echo Clocks .............................................................. 10 PLL ............................................................................ 10 Application Example ...................................................... 10 Truth Table ...................................................................... 11 Burst Address Table (CY7C1518KV18, CY7C1520KV18) ................................ 11 Write Cycle Descriptions ............................................... 11 Write Cycle Descriptions ............................................... 12 Write Cycle Descriptions ............................................... 12 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13 Disabling the JTAG Feature ...................................... 13 Test Access Port—Test Clock................................... 13 Test Mode Select (TMS) ........................................... 13 Test Data-In (TDI) ...

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... Pin Configuration The pin configurations for CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and CY7C1520KV18 follow DQ4 DQ5 H DOFF V V REF DDQ DQ6 DQ7 R TDO TCK DQ4 DQ5 H DOFF V V REF DDQ DQ6 DQ7 R TDO TCK A Note 1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. ...

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... Pin Configuration (continued) The pin configurations for CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and CY7C1520KV18 follow DQ9 DQ10 DQ11 F NC DQ12 DQ13 H DOFF V V REF DDQ DQ14 L NC DQ15 DQ16 DQ17 R TDO TCK NC/144M DQ27 DQ18 DQ28 D NC DQ29 DQ19 DQ20 F NC DQ30 DQ21 ...

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... CY7C1518KV18 – the input to the burst counter. These are incremented in a linear fashion internally. 22 address inputs are needed to access the entire memory array. CY7C1520KV18 – the input to the burst counter. These are incremented in a linear fashion internally. 21 address inputs are needed to access the entire memory array. All the address inputs are ignored when the appropriate port is deselected ...

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... Ground for the device Power Supply Power supply inputs for the outputs of the device. DDQ Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Pin Description output impedance are set to 0.2 x RQ, where resistor connected [x:0] , which enables the DDQ Page [+] Feedback ...

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... Functional Overview The CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and CY7C1520KV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and a half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to V behaves in DDR-I mode with a read latency of one clock cycle. ...

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... Echo Clock1/Echo Clock#1 Echo Clock2/Echo Clock#2 Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 PLL These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the PLL is locked after 20 μ ...

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... Device powers up deselected with the outputs in a tristate condition CY7C1518KV18 and CY7C1520KV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses sequence in the burst. On CY7C1516KV18 and CY7C1527KV18, “A1” represents A + ‘0’ and “A2” represents A + ‘1’. ...

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... L–H – No data is written into the device during this portion of a write operation. H – L–H No data is written into the device during this portion of a write operation. Write Cycle Descriptions The write cycle description table for CY7C1520KV18 follows. BWS BWS BWS BWS ...

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... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Instruction Register Three-bit instructions are serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in page 16 ...

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... TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. ...

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... The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 [9] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- ...

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... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the 11. Overshoot: V (AC) < 0. (Pulse width less than t IH DDQ 12. All voltage referenced to Ground. Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 0 Bypass Register Instruction Register ...

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... CS CH 14. Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Description [14] Figure 2. TAP Timing and Test Conditions 0 Ω ...

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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Value CY7C1527KV18 CY7C1518KV18 000 000 00000110100 00000110100 ...

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... Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D ...

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... DDQ DOFF Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 PLL Constraints PLL uses K clock as its synchronizing input. The input must ■ have low phase jitter, which is specified as t The PLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the PLL is enabled, then the ■ ...

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... RQ < 350 Ω. 17. Outputs are impedance controlled DDQ 18. V (min whichever is larger, V REF DDQ Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Neutron Soft Error Immunity Parameter LSBU LMBU DD + 0.3 V DDQ SEL + 0 LMBU or SEL events occurred during testing; this column represents a 2 statistical χ ...

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... DC Electrical Characteristics [12] Over the Operating Range Parameter Description [19 operating supply DD DD Note 19. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Test Conditions V = Max, 333 MHz (x8 mA, OUT (x9 1/t MAX CYC (x18) ...

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... Description I Automatic power down SB1 current AC Electrical Characteristics [11] Over the Operating Range Parameter Description V Input HIGH voltage IH V Input LOW voltage IL Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Test Conditions Max V , 333 MHz (x8) DD Both Ports Deselected, (x9) ≥ V ≤ 1/t ...

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... Note 20. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0. levels of 0. 1.25 V, and output loading of the specified I Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Test Conditions T = 25° MHz 1 Test Conditions ...

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... When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated and outputs data with the output timings of that frequency range. 22. This part has an internal voltage regulator; t POWER Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 333 MHz 300 MHz Min Max Min Max Min Max Min Max Min Max [22] 1 – ...

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... CHZ CLZ 25. At any voltage and temperature t is less than t CHZ Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 333 MHz 300 MHz Min Max Min Max Min Max Min Max Min Max – 0.45 – 0.45 – ...

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... Outputs are disabled (High-Z) one clock cycle after a NOP. 28. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 [26, 27, 28] NOP NOP ...

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... CY7C1520KV18-300BZXI 250 CY7C1518KV18-250BZC CY7C1520KV18-250BZC CY7C1518KV18-250BZXC CY7C1520KV18-250BZXC CY7C1518KV18-250BZI CY7C1520KV18-250BZI CY7C1518KV18-250BZXI CY7C1520KV18-250BZXI 200 CY7C1520KV18-200BZC Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 www.cypress.com Package Diagram Package Type 51-85180 165-ball FBGA ( 1.4 mm) 51-85180 165-ball FBGA ( 1.4 mm) Pb-Free 51-85180 165-ball FBGA ( 1.4 mm) 51-85180 165-ball FBGA ( 1.4 mm) Pb-Free 51-85180 165-ball FBGA ( ...

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... Ordering Code Definition CY 7C 15XX K V18 - XXX XXX X Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Temperature Range Commercial Industrial Package Type: XXX = BZ or BZX BZ = 165-ball FBGA BZX = 165-ball FBGA (Pb-free) Frequency range: 333 MHz or 300 MHz or 250 MHz or 200 MHz V18 = 1.8 V ...

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... Package Diagram Figure 6. 165-Ball FBGA ( 1.4 mm), 51-85180 TOP VIEW PIN 1 CORNER 13.00±0.10 SEATING PLANE C Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 0.15(4X) BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. Ø0.50 -0.06 (165X) +0. 1.00 5.00 10.00 13.00±0.10 NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0 ...

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... TAP test access port TCK test clock TMS test mode select TDI test data-in TDO test data-out Document Number: 001-00437 Rev. *J CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes µs micro seconds ...

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... Document History Page Document Title: CY7C1516KV18/CY7C1527KV18/CY7C1518KV18/CY7C1520KV18, 72-Mbit DDR II SRAM 2-Word Burst Architecture Document Number: 001-00437 Orig. of Submission Rev. ECN No. Change Date ** 374703 SYT See ECN *A 1103864 VKN See ECN *B 1699246 VKN/AESA See ECN *C 1939726 VKN/AESA See ECN *D 2606839 VKN/PYRS 11/13/08 *E 2681899 VKN/PYRS ...

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... QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 cypress.com/go/plc Revised April 10, 2011 PSoC Solutions psoc ...