PC28F00AP33TFA NUMONYX, PC28F00AP33TFA Datasheet

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... Individual zero-latency block locking — Individual block lock-down capability — Password Access feature — One-Time Programmable Register: — 64 OTP bits, programmed with unique information by Numonyx — 2112 OTP bits, available for customer programming Software: — 25µs (Typ) program suspend — 30µs (Typ) erase suspend ® ...

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... Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. ...

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... P33-65nm Contents 1.0 Functional Description ............................................................................................... 7 1.1 Introduction ....................................................................................................... 7 1.2 Overview ........................................................................................................... 7 1.3 Virtual Chip Enable Description (2-Gbit) ................................................................. 8 1.4 Memory Map....................................................................................................... 9 2.0 Package Information ............................................................................................... 11 2.1 56-Lead TSOP Package (512-Mbit, 1-Gbit) ............................................................ 11 2.2 64-Ball Easy BGA Package (512-Mbit, 1-Gbit, 2-Gbit) ............................................. 12 3.0 Pinouts and Ballouts................................................................................................ 14 4.0 Signals .................................................................................................................... 16 4 ...

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Lock Block .............................................................................................33 10.1.2 Unlock Block ..........................................................................................33 10.1.3 Lock-Down Block ....................................................................................33 10.1.4 Block Lock Status ...................................................................................33 10.1.5 Block Locking During Suspend ..................................................................34 10.2 Selectable OTP Blocks ........................................................................................35 10.3 Password Access................................................................................................35 11.0 Register ...................................................................................................................36 11.1 Status Register (SR) ..........................................................................................36 11.2 ...

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... Functional Description 1.1 Introduction This document provides information about the Numonyx memory and describes its features, operations, and specifications. P33-65nm is the latest generation of Numonyx embedded flash market segment, offered in 64-Mbit up through 2-Gbit. This document covers specifically 512-Mbit, 1-Gbit, 2-Gbit product information. Benefits include more density in less space, high-speed interface NOR device on TSOP package, and support for code and data storage ...

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Virtual Chip Enable Description (2-Gbit) The P33-65nm device employs a Virtual Chip Enable to combine two 1-Gbit dies with a common chip enable, CE#, for Easy BGA, Address A27 is then used to select between the die pair with ...

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... P33-65nm 1.4 Memory Map Figure 1: P33-65nm Memory Map (512-Mbit and 1-Gbit Densities) 3FF0000 -3FFFFFF 64 - Kword Block 64 - Kword Block 1FF0000 -1FFFFFF 64 - Kword Block FF0000 -FFFFFF 64 - Kword Block 020000 -02FFFF 64 - Kword Block 010000 -01FFFF 00C000 -00FFFF 16 - Kword Block 008000 -00BFFF 16 - Kword Block 16 - Kword Block ...

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... Figure 2: P33-65nm Memory Map (2-Gbit) 7FF0000 -7FFFFFF 4010000 -401FFFF 4000000 -400FFFF 3FF0000 -3FFFFFF 1FF0000 -1FFFFFF FF0000-FFFFFF 020000 -02FFFF 010000 -01FFFF 000000 -00FFFF Datasheet 27:1 ] 2-Gbit (1-Gbit/1-Gbit) 64- Kword Block 64- Kword Block 64- Kword Block 64- Kword Block 64- Kword Block 64- Kword Block 64- Kword Block 64- Kword Block ...

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P33-65nm 2.0 Package Information 2.1 56-Lead TSOP Package (512-Mbit, 1-Gbit) Figure 3: TSOP Mechanical Specifications Z See Notes 1 and 3 Pin 1 See Detail A Detail A Table 2: TSOP Package Dimensions (Sheet Product Information Symbol ...

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Table 2: TSOP Package Dimensions (Sheet Product Information Symbol Lead Count N Lead Tip Angle θ Seating Plane Coplanarity Y Lead to Package Offset Z Notes: 1. One dimple on package denotes Pin two ...

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P33-65nm Table 3: Easy BGA Package Dimensions for 8x10x1.2 mm (Sheet Product Information Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E ...

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... A25 is valid for 512-Mbit densities and above; otherwise connect (NC). 4. A26 is valid for 1-Gbit density and above; otherwise connect (NC). 5. One dimple on package denotes Pin 1 which will always be in the upper left corner of the package, in reference to the product mark. Datasheet 14 Flash Memory 56-Lead TSOP Pinout Top View P33-65nm 56 WAIT 55 ...

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P33-65nm Figure 6: 64-Ball Easy BGA Ballout (512-Mbit, 1-Gbit, 2-Gbit VPP B A2 VSS A9 CE A10 A12 A11 RST# VCCQ E DQ8 DQ1 DQ9 DQ3 ...

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... TSOP: ADV# must be tied to VSS or held low throughout the read cycle. WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through. CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When ...

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... P33-65nm Table 4: TSOP and Easy BGA Signal Descriptions (Sheet Symbol Type RESERVED FOR FUTURE USE: Reserved by Numonyx for future device functionality and RFU — enhancement. These should be treated in the same way as a Don’t Use (DU) signal. DU — DON’T USE: Do not connect to any other signal, or power supply; must be left floating. ...

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Bus Operations CE# low and RST# high enable device read operations. The device internally decodes upper address inputs to determine the accessed block. ADV# low opens the internal address latches. OE# low activates the outputs and gates selected data ...

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... P33-65nm In asynchronous page mode, sixteen data words are “sensed” simultaneously from the flash memory array and loaded into an internal page buffer. The buffer word corresponding to the initial address on the address bus is driven onto DQ[15:0] after the initial access delay. The lowest four address bits determine which word of the 16-word page is output from the data buffer at any given time ...

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... CPU initialization may occur because the flash memory may be providing status information rather than array data. Flash memory devices from Numonyx allow proper CPU initialization following a system reset through the use of the RST# input. After initial power-up or reset, the device defaults to asynchronous Read Array mode, and the Status Register is set to 0x80 ...

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... The flash Command User Interface (CUI) provides control of all read, write, and erase operations. The on-chip WSM manages all block-erase and word-program algorithms. Device commands are written to the CUI to control all flash memory device operations. The CUI does not occupy an addressable memory location the mechanism through which the flash device is controlled ...

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Table 6: Command Codes and Definitions (Sheet Mode Code Device Mode Program or Erase 0xB0 Suspend Suspend 0xD0 Suspend Resume 0x60 Block lock Setup 0x01 Block lock Protection 0xD0 Block Unlock 0x2F Block Lock-Down OTP Register or ...

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... DBA = Device Base Address.(Note: needed for dual-die 2-Gbit device.) DnA = Address within the device Identification code address offset. CFI-A = Read CFI address offset Word address of memory location to be written Address within the block. OTP-RA = OTP Register address. LRA = Lock Register address. ...

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... Data(x16) 0x89h Table 9 ID (See ) Lock Bit: DQ0 = 0b0 DQ0 = 0b1 DQ1 = 0b0 DQ1 = 0b1 RCR Contents GPR data PR-LK0 Numonyx Factory OTP Register data User OTP Register data Apr 2010 Order Number: 208043-05 ...

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... Item Lock Register 1 128-bit User-Programmable OTP registers Notes: 1. BBA = Block Base Address. 2. DBA = Device base Address, Numonyx reserves other configuration address locations P33-65nm, the GPR is used as read out register for Extended Function Interface command. Table 9: Device ID codes ID Code Type Device Density ...

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... Programming the flash memory array changes “ones” to “zeros”. Memory array bits that are zeros can be changed to ones only by erasing the block. The Status Register can be examined for programming progress and errors by reading at any address ...

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... After the last data is written to the buffer, the Buffered Programming Confirm command must be issued to the original block address. The WSM begins to program buffer contents to the flash memory array command other than the Buffered Programming Confirm command is written to the device, a command sequence error occurs and SR[7,5,4] are set ...

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... BEFP programs one block at a time; all buffer data must fall within a single block. Suspend BEFP cannot be suspended. Programming the flash Programming to the flash memory array can occur only when the buffer is full. memory array Notes: 1. Some degradation in performance may occur is this limit is exceeded, but the internal algorithm continues to work properly ...

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... During the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 512, the remaining buffer locations must be filled with 0xFFFF ...

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When a programming operation is executing, issuing the Program Suspend command requests the WSM to suspend the programming algorithm at ...

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... During a block erase, the WSM executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array changes “zeros” to “ones”. Memory array block that are ones can be changed to zeros only by programming the block. ...

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... Erase Suspend Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows data to be accessed from memory locations other than the one being erased. The Erase Suspend command can be issued to any device address. A block erase operation can be suspended to perform a word or buffer program operation read operation within any block except the block that is erase suspended (see Figure 36, “ ...

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... Block Locking Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be programmed or erased; they can only be read. ...

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Figure 9: Block Locking State Diagram Note: LK: Lock Setup Command, 60h; LK/D0h: Unlock Command; ...

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... Selectable OTP Blocks P33-65nm provides the backward compatible One Time Programming permanent block lock security feature. Blocks from the main array can be optionally configured as OTP. Ask your local Numonyx Sales representative for details about these selectable OTP implementations. 10.3 Password Access Password Access is a security enhancement offered on P33-65nm device ...

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Register When non-array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined. When a non-array read operation occurs as synchronous burst mode, the same word of data requested will ...

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P33-65nm 11.2 Read Configuration Register (RCR)(Easy BGA) The RCR is a 16-bit read/write register used to select the read mode (synchronous or asynchronous), and to configure synchronous burst characteristics of the device. To modify RCR settings, use the Configure Read ...

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Table 13: Read Configuration Register Description (Sheet Burst Wrap (BW) 3 2:0 Burst Length (BL[2:0]) 11.2.1 Read Mode (RCR.15) The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation for the device. When the RM ...

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P33-65nm Figure 10: First-Access Latency Count CLK [C] Valid A ddress [A] Address ADV# [V] Code 0 (Reserved) Valid DQ [D/Q] Output 15-0 Code 1 (Reserved ) DQ [D/Q] 15-0 Code 2 DQ [D/Q] 15-0 Code 3 DQ [D/Q] 15-0 ...

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Figure 11: Example Latency Count Setting Using Code 3 CLK CE# ADV# A[MAX:0] A[MAX:1] D[15:0] 11.2.3 End of Word Line (EOWL) Considerations The delay may occur when a burst sequence access crosses a 16-word boundary. That is, A[4:1] of start ...

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P33-65nm Table 15: End of Wordline Data and WAIT state Comparison Latency Count Data States 1 Not Supported Not Supported ...

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Table 17: Burst Sequence Word Ordering Start Burst Addr. Wrap 4-Word Burst (DEC) (RCR.3) (BL[2:0] = 0b001 0-1-2 1-2-3 2-3-0 3-0-1 ...

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... Each OTP Register can be individually locked. The first 128-bit OTP Register is comprised of two 64-bit (8-word) segments. The lower 64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit number. The upper 64-bit segment, as well as the other sixteen 128-bit OTP Registers, are blank ...

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Figure 13: OTP Register Map 0x109 0x102 0x91 0x8A 0x89 0x88 0x85 0x84 0x81 0x80 11.3.1 Reading the OTP Registers The OTP Registers can be read from OTP-RA address. To read the OTP Register, first issue the Read Device Identifier ...

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... Identifier Information” on page Bit 0 of Lock Register 0 is already programmed during the manufacturing process at Numonyx factory, locking the lower half segment of the first 128-bit OTP Register. Bit 1 of Lock Register 0 can be programmed by the user to lock the upper half of the first 128-bit OTP Register. When programming Bit 1 of Lock Register 0, all other bits need to be left as ‘ ...

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... Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected ...

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... Two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. Because flash memory devices draw their power from VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to ground. High-frequency, inherently low-inductance capacitors should be placed as close as possible to package leads ...

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Maximum Ratings and Operating Conditions 13.1 Absolute Maximum Ratings Warning: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Table 19: Absolute Maximum Ratings Parameter Temperature under bias Storage temperature Voltage ...

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P33-65nm 14.0 Electrical Specifications 14.1 DC Current Characteristics Table 21: DC Current Characteristics (Sheet Sym Parameter 512-Mbit/ 1-Gbit I Input Load Current LI 2-Gbit Output Leakage 512-Mbit/ Current 1-Gbit I LO DQ[15:0], WAIT 2-Gbit 512-Mbit 1-Gbit I ...

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Table 21: DC Current Characteristics (Sheet Sym Parameter I VPP Blank Check PPBC Notes: 1. All currents are RMS unless noted. Typical values at typical VCC the average current measured over any 5ms ...

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P33-65nm 15.0 AC Characteristics 15.1 AC Test Conditions Figure 15: AC Input/Output Reference Waveform V CCQ Input V /2 CCQ 0V Note: AC test inputs are driven at VCCQ for Logic "1" and 0 V for Logic "0." Input/output timing ...

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Figure 17: Clock Input AC Waveform CLK [C] 15.2 Capacitance Table 24: Capacitance Sym Parameter Address, Data, CE#, C Input Capacitance WE#, OE#, RST#, IN CLK, ADV#, WP# C Output Capacitance Data, WAIT OUT Note: Sampled, not 100% tested. Datasheet ...

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P33-65nm 15.3 AC Read Specifications Table 25: AC Read Specifications - (Sheet Num Symbol Asynchronous Specifications R1 t Read cycle time AVAV R2 t Address to output valid AVQV R3 t CE# low to output valid ELQV ...

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Table 25: AC Read Specifications - (Sheet Num Symbol Synchronous Specifications (Easy BGA) R301 t Address setup to CLK AVCH/L R302 t ADV# low setup to CLK VLCH/L R303 t CE# low setup to CLK ELCH/L R304 ...

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P33-65nm Figure 19: Asynchronous Single-Word Read for Easy BGA (ADV# Latch) Address [A] A[4:1][A] R101 R 105 R106 R 104 ADV#[V] CE# [E] OE# [G] R15 WAIT [T] Data [D/Q] Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT ...

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... This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by CE# deassertion after the first word in the burst. Figure 22: Continuous Burst Read, showing an Output Delay Timing for Easy BGA ...

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P33-65nm Figure 23: Synchronous Burst-Mode Four-Word Read Timing for Easy BGA R302 R301 R306 CLK [C] R2 R101 Address [A] A R105 R105 R106 R102 ADV# [V] R303 CE# [E] OE# [G] R15 WAIT [T] R7 Data [D/Q] Note: WAIT ...

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Table 26: AC Write Specifications (Sheet Num Symbol Write to Synchronous Read Specifications W19 t WE# high to Clock valid WHCH/L W20 t WE# high to ADV# high WHVH W28 t WE# high to ADV# low WHVL ...

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P33-65nm Figure 25: Asynchronous Read-to-Write Timing W5 Address [A] W2 CE# [E] WE# [W] OE# [G] Data [D/Q] W1 RST# [P] Note: WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserted. Figure 26: Write-to-Asynchronous ...

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Figure 27: Synchronous Read-to-Write Timing R301 R302 R306 CLK [C] R2 R101 Address [A] R105 R105 R106 R102 ADV# [V] R303 R3 CE# [E] OE# [G] WE#[W] WAIT [T] Data [D/Q] Note: WAIT shown deasserted and High-Z per OE# deassertion ...

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P33-65nm Program and Erase Characteristics 15.5 Table 27: Program and Erase Specifications Num Symbol Parameter Program W200 t Single word PROG/W Time Aligned 32-Wd, BP time (32 Words) Aligned 64-Wd, BP time (64 Word) Program Aligned 128-Wd, BP time W250 ...

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... The last digit is randomly assigned to cover packing media and/or features or other specific configuration Table 28: Valid Combinations for P33 65nm Products 512-Mbit PC28F512P33EF* PC28F512P33BF* PC28F512P33TF* JS28F512P33EF* JS28F512P33BF* JS28F512P33TF* Note: For leaded package option, please contact your Numonyx sales representative for detail. For further information on ordering products or for product part numbers, go to: http://www.numonyx.com/en-US/MemoryProducts/Pages/PartNumberLookup.aspx Datasheet ...

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P33-65nm Appendix A Supplemental Reference Information A.1 Common Flash Interface The Common Flash Interface (CFI) is part of an overall specification for multiple command-set and control-interface descriptions. This appendix describes the database structure containing the data returned by a read ...

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... BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 32-KWord). 3. Offset 15 defines “P” which points to the Primary Numonyx-specific Extended Query Table. A.1.3 Read CFI Identification String The Identification String provides verification that the component supports the Common Flash Interface specification ...

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P33-65nm Table 32: CFI Identification Offset Length 10h 3 Query-unique ASCII string “QRY”. Primary Vendor command set and control interface ID code. 13h 2 16-bit ID code for Vendor-specified algorithms. 15h 2 Extended Query Table primary algorithm address. Alternate vendor ...

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... A.1.4 Numonyx-Specific Extended Query Table Table 34: Device Geometry Definition Offset Length 27h 1 “n” such that device size = 2 Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: ...

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... P33-65nm A.1.5 Numonyx-Specific Extended Query Table Table 35: Primary Vendor-Specific Extended Query Offset Length P=10Ah (P+0)h Primary extended query table (P+1)h 3 Unique ASCII string “PRI” (P+2)h (P+3)h 1 Major version number, ASCII (P+4)h 1 Minor version number, ASCII (P+5)h 4 Optional feature and command support (1=yes, 0=no) (P+6)h bits 10-31 are reserved ...

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Table 36: OTP Register Information Offset (1) Length P = 10Ah (Optional flash features and commands) (P+E)h 1 Number of Protection register fields in JEDEC ID space. “00h,” indicates that 256 protection fields are available (P+F)h 4 Protection Field 1: ...

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P33-65nm Table 37: Burst Read Information (1) Offset Length P = 10Ah (Optional flash features and commands) (P+1D)h 1 Page Mode Read capability bits 0–7 = “n” such that 2 read-page bytes. See offset 28h for device w ord w ...

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Table 39: Partition Region 1 Information (Sheet Offset ( 10Ah Bottom Top (P+24)h (P+24)h Data size of this Parition Region Information field (P+25)h (P+25)h (# addressable locations, including this field) (P+26)h (P+26)h Number of identical ...

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P33-65nm Table 40: Partition Region 1 Information (Sheet Offset ( 10Ah Bottom Top (P+2C)h (P+2C)h Partition Region 1 Erase Block Type 1 Information (P+2D)h (P+2D)h bits 0– y identical-size erase blks ...

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Table 41: Partition and Erase Block Region Information Add. Top 12D: --01 12E: --24 12F: --00 130: --01 131: --00 132: --11 133: --00 134: --00 135: --02 136: --FE 137: --01 138: --00 139: --02 13A: --64 13B: --00 ...

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... CFI Link Field bit definitions Bits 0:9 = Address offset (within 32Mbit segment) of referenced CFI table Bits 10:27 = nth 32Mbit segment of referenced CFI table Bits 28:30 = Memory Type Bit 31 = Another CFI Link field immediately follows 1 CFI Link Field Quantity Subfield definitions Bits 3:0 = Quantity field (n such that n+1 equals quantity) Bit 4 = Table & ...

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A.2 Flowcharts Figure 30: Word Program Flowchart Start Command Cycle - Issue Program Command - Address = location to program - Data = 0x40 Data Cycle - Address = location to program - Data = Data to program Check Ready ...

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P33-65nm Figure 31: Program Suspend/Resume Flowchart Start Device No Supports Buffer Writes ? Yes Set Timeout or Loop Counter Get Next Target Address Issue Write to Buffer Command E8h Block Address Read Status Register Block Address (note 7) Is WSM ...

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Figure 32: Buffer Program Flowchart Start Device No Supports Buffer Writes ? Yes Set Timeout or Loop Counter Get Next Target Address Issue Write to Buffer Command E8h Block Address Read Status Register Block Address (note 7) Is WSM Ready ...

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P33-65nm Figure 33: BEFP Flowchart Setup Phase Start Issue BEFP Setup Cmd (Data = 0x80) Issue BEFP Confirm Cmd (Data = 00D0h) BEFP Setup Delay Read Status Register Yes (SR.7=0) BEFP Setup Done ? No (SR.7=1) SR Error Handler (User-Defined) ...

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Figure 34: Block Erase Flowchart Start Command Cycle - Issue Erase command - Address = Block to be erased - Data = 0x20 Confirm Cycle - Issue Confirm command - Address = Block to be erased - Data = Erase ...

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P33-65nm Figure 35: Block Lock Operations Flowchart Start Lock Setup Write 60h Block Address Lock Confirm Write 01 ,D0,2Fh Block Address Read ID Plane Write 90h Read Block Lock Status Locking No Change ? Yes Read Array Write FFh Any ...

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Figure 36: Erase Suspend/Resume Flowchart Start Write 0 x70 , (Read Status ) Same Partition Write 0xB0, (Erase Suspend ) Any Address Read Status Register Read Read or Program Program ...

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P33-65nm Figure 37: OTP Register Programming Flowchart - Read Status Register Command not required - Perform read operation - Read Ready Status on signal SR.7 - Toggle CE# or OE# to update Status Register - See Status Register Flowchart Datasheet ...

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Figure 38: Status Register Flowchart - Issue Status Register Command - Address = any device address - Data = 0x70 - Read Status Register SR[7:0] - Set/Reset by WSM - Set by WSM - Reset by user - See Clear ...

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P33-65nm A.3 Write State Machine Show here are the command state transitions (Next State Table) based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read state (Read ...

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Table 43: Next State Table for P3x-65nm (Sheet Current Chip State (FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) Setup (8) BP Load 1 (8) BP Load 2 Buffer BP Confirm Ready (Error [Botch]) Pgm ...

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P33-65nm Table 43: Next State Table for P3x-65nm (Sheet Current Chip State (FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) EFI Setup Sub-function Setup Sub-op-code Sub-function Load 2 in Erase Suspend if word count >0, ...

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Table 44: Output Next State Table for P3x-65nm Current Chip State (FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP Setup, Load 1, Load 2 BP Setup, ...

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... Two bytes, or sixteen bits 1024 bits 1024 bytes 1024 words 1,048,576 bits 1,048,576 bytes 1,048,576 words 1,000 1,000,000 A group of bits, bytes, or words within the flash memory array that erase simultaneously. An array block that is usually used to store code and/or data. Apr 2010 Order Number:208043-05 ...

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... Align flowchart of block locking operation as same as 130nm. Add note 7 to flowchart of Buffer program. Update Ordering Information. Update RCR.7 in page 37 Add 2-Gbit density related information such as memory map, CFI, ordering information current spec, capacitance, dual-die configuration and Device ID note etc. Nov 2009 03 Update suspend latency spec. ...