74AUP2G06GF,132 NXP Semiconductors, 74AUP2G06GF,132 Datasheet

IC GATE NOR DUAL 2INPUT XSON8

74AUP2G06GF,132

Manufacturer Part Number
74AUP2G06GF,132
Description
IC GATE NOR DUAL 2INPUT XSON8
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74AUP2G06GF,132

Number Of Circuits
2
Logic Family
74AUP
Propagation Delay Time
4 ns, 4.3 ns, 6.3 ns, 7.8 ns, 12 ns
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Package / Case
XSON-6
Mounting Style
SMD/SMT
Operating Supply Voltage
0.8 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-5398-2
1. General description
2. Features and benefits
The 74AUP2G06 provides two inverting buffers with open-drain output. The output of the
device is an open drain and can be connected to other open-drain outputs to implement
active-LOW wired-OR or active-HIGH wired-AND functions.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
This device ensures a very low static and dynamic power consumption across the entire
V
This device is fully specified for partial Power-down applications using I
The I
the device when it is powered down.
CC
74AUP2G06
Low-power dual inverter with open-drain output
Rev. 3 — 26 October 2010
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD 78B Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
OFF
range from 0.8 V to 3.6 V.
OFF
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114F Class 3A. Exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
circuitry provides partial Power-down mode operation
circuitry disables the output, preventing the damaging backflow current through
CC
range from 0.8 V to 3.6 V.
CC
= 0.9 μA (maximum)
CC
Product data sheet
OFF
.

Related parts for 74AUP2G06GF,132

74AUP2G06GF,132 Summary of contents

Page 1

Low-power dual inverter with open-drain output Rev. 3 — 26 October 2010 1. General description The 74AUP2G06 provides two inverting buffers with open-drain output. The output of the device is an open drain and can be connected to other ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range −40 °C to +125 °C 74AUP2G06GW −40 °C to +125 °C 74AUP2G06GM −40 °C to +125 °C 74AUP2G06GF −40 °C to +125 °C 74AUP2G06GN −40 °C to +125 °C 74AUP2G06GS 4. Marking Table 2. Marking Type number ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74AUP2G06 GND 001aal424 Fig 4. Pin configuration SOT363 6.2 Pin description Table 3. Pin description Symbol Pin 1A GND 2 1Y Functional description 7.1 Function table [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level high-impedance OFF-state. 74AUP2G06 ...

Page 4

... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...

Page 5

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level output voltage OL I input leakage current I I OFF-state output current OZ I power-off leakage current OFF ΔI additional power-off OFF leakage current I supply current CC ΔI ...

Page 6

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I OFF-state output current OZ I power-off leakage current OFF ΔI additional power-off OFF leakage current I supply current CC ΔI additional supply current CC = −40 °C to +125 °C T amb ...

Page 7

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation delay nA to nY; see propagation delay nA to nY; see propagation delay nA to nY; see propagation delay nA to nY; see 74AUP2G06 Product data sheet Low-power dual inverter with open-drain output ...

Page 8

... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions pF and power dissipation MHz capacitance [1] All typical values are measured at nominal V [ the same as t and PZL PLZ [ used to determine the dynamic power dissipation (P PD × ...

Page 9

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 8. Test circuit for measuring switching times Table 10. ...

Page 10

... NXP Semiconductors 13. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 1.1 0.30 0.25 mm 0.1 0.8 0.20 0.10 OUTLINE VERSION IEC SOT363 Fig 9. Package outline SOT363 (SC-88) 74AUP2G06 Product data sheet scale 2.2 1.35 2 ...

Page 11

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. 6× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 12

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 11 ...

Page 13

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 14

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 15

... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 12. Revision history Document ID Release date 74AUP2G06 v.3 20101026 • Modifications: Added type number 74AUP2G06GN (SOT1115/XSON6 package). ...

Page 16

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 17

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74AUP2G06 Product data sheet Low-power dual inverter with open-drain output 16 ...

Page 18

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms ...

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