D2-45157-QR-T Intersil, D2-45157-QR-T Datasheet - Page 12

• Manufacturer Part Number: D2-45157-QR-T
• Description: IC DGTL AMP PWM CTRLR 68QFN
• Manufacturer: Intersil
• Series: D2Audio™r
• Type: Class Dr

Specifications of D2-45157-QR-T

• Output Type: 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 30W x 2 @ 8 Ohm
• Voltage - Supply: 9 V ~ 26 V
• Mounting Type: Surface Mount
• Package / Case: 68-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Pin Description
PIN
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
(Note 13) TYPE
PWMGND
PWMVDD
PLLGND
PLLVDD
VDDHV
HVDDB
HGNDB
HGNDA
HVDDA
HSBSB
HSBSA
REG5V
OCFG1
OCFG0
NAME
XTALO
LINER
LINEL
XTALI
OUTB
OUTA
nPDN
IREF
PIN
GND
GND
O
O
O
O
P
P
P
P
P
P
P
P
P
P
I
I
I
I
I
I
VOLTAGE
LEVEL
+HV
12
(V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.8
1.8
1.8
1.8
HV
HV
HV
HV
HV
HV
HV
HV
5
-
(Continued)
Overcurrent reference analog input. Used in setting the overcurrent error detect externally-
set threshold. The pin needs to be connected to a 100kΩ resistor to ground to set the
overcurrent threshold according to the specified limits.
High Voltage internal driver supply power. All of the HVDD[A:D] pins and the VDDHV pin
connect to the system “HV” power source. The internal +5V supply regulators also operate
from this VDDHV input.
5V internal regulator filter connect. A +5V supply is internally generated from the voltage
source provided at the VDD pin. REG5V is used for external connection of a decoupling
capacitor.
Output stage B high voltage supply power. A separate power pin connection is provided for
each of the output stages. All of the HVDD[A:D] pins and the VDDHV pin connect to the
system “HV” power source.
Output stage B high voltage supply ground. A separate ground pin connection is provided
for each of the output stages. All of the HGND[A:D] pins connect to system “HV” power
ground (also see Note 15).
PWM power amplifier output, channel B.
High-side boot strap input, output channel B. Capacitor couples to OUTB amplifier output.
High-side boot strap input, output channel A. Capacitor couples to OUTA amplifier output.
PWM power amplifier output, channel A.
Output stage A high voltage supply ground. A separate ground pin connection is provided
for each of the output stages. All of the HGND[A:D] pins connect to system “HV” power
ground (also see Note 15).
Output stage A high voltage supply power. A separate power pin connection is provided for
each of the output stages. All of the HVDD[A:D] pins and the VDDHV pin connect to the
system “HV” power source.
Power-down and mute input. Active low. When this input is low, all 4 outputs become
inactive and their output stages float, and their output is muted. Internal logic and other
references remain active during this power-down state.
“Right” channel PWM output, with 16mA drive strength. Connects to filter network for
supplying line-level analog output.
“Left” channel PWM output, with 16mA drive strength. Connects to filter network for
supplying line-level analog output.
Output configuration control select. OCFG0 and OCFG1 are logic inputs to select the output
configuration mode of the output stages. Connects to either PWMGND ground or PWMVDD
(+3.3V) through nominal 10kΩ resistor to select output configuration.
Output configuration control select. OCFG0 and OCFG1 are logic inputs to select the output
configuration mode of the output stages. Connects to either PWMGND ground or PWMVDD
(+3.3V) through nominal 10kΩ resistor to select output configuration.
PWM output pin ground. Internally connected to RGND.
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally
connected to RVDD.
PLL Analog ground. Should be tied to low voltage ground (CGND, RGND) through single
point connection to isolate ground noise on board and minimizing affecting of PLL.
Crystal oscillator analog input port.
Crystal oscillator analog output port. (This output drives the crystal and XTALO does not
have a drive strength specification.)
PLL Analog power, 1.8V.
D2-45057, D2-45157
DESCRIPTION
July 29, 2010
FN6785.0