STM32F101VCT6TR STMicroelectronics, STM32F101VCT6TR Datasheet - Page 66

• Manufacturer Part Number: STM32F101VCT6TR
• Description: MCU ARM 32BIT 256KB FLSH 100LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F101VCT6TR

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 36MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 80
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Electrical characteristics
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Figure 28. Synchronous non-multiplexed PSRAM write timings
Table 38.
1. C
2. Based on characterization, not tested in production.
t
t
t
t
t
t
t
t
t
t
t
t
t
w(CLK)
d(CLKL-NExL)
d(CLKH-NExH)
d(CLKL-NADVL)
d(CLKL-NADVH)
d(CLKL-AV)
d(CLKH-AIV)
d(CLKL-NWEL)
d(CLKH-NWEH)
d(CLKL-Data)
su(NWAITV-CLKH)
h(CLKH-NWAITV)
d(CLKL-NBLH)
FSMC_D[15:0]
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FSMC_A[25:0]
FSMC_NADV
Symbol
L
FSMC_NWE
FSMC_NBL
FSMC_CLK
= 15 pF.
FSMC_NEx
t d(CLKL-NADVL)
t d(CLKL-NExL)
Synchronous non-multiplexed PSRAM write timings
t w(CLK)
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK high to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
FSMC_CLK low to FSMC_NADV high
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
FSMC_CLK high to FSMC_Ax invalid (x = 16...25)
FSMC_CLK low to FSMC_NWE low
FSMC_CLK high to FSMC_NWE high
FSMC_D[15:0] valid data after FSMC_CLK low
FSMC_NWAIT valid before FSMC_CLK high
FSMC_NWAIT valid after FSMC_CLK high
FSMC_CLK low to FSMC_NBL high
t d(CLKL-AV)
t d(CLKL-NWEL)
Doc ID 14610 Rev 7
t su(NWAITV-CLKH)
t d(CLKL-Data)
t d(CLKL-NADVH)
Parameter
Data latency = 1
t w(CLK)
STM32F101xC, STM32F101xD, STM32F101xE
D1
t h(CLKH-NWAITV)
t d(CLKH-NExH)
t d(CLKH-NWEH)
t d(CLKH-AIV)
27.7
T
5
T
T
7
2
1
HCLK
CK
HCLK
t d(CLKL-NBLH)
(1)(2)
BUSTURN = 0
t d(CLKL-Data)
D2
Min
+ 2
+ 2
+ 1
2
4
0
1
6
Max
ai14993e
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit