STM8S207C8T3 STMicroelectronics, STM8S207C8T3 Datasheet - Page 21

• Manufacturer Part Number: STM8S207C8T3
• Description: IC MCU 8BIT 64KB FLASH 48LQFP
• Manufacturer: STMicroelectronics
• Series: STM8Sr

Specifications of STM8S207C8T3

• Featured Product: STM32 Cortex-M3 Companion Products
• Core Processor: STM8
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1.5K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.95 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LFQFP
• Core: STM8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STM8S207xx, STM8S208xx
4.14.3
Asynchronous communication (UART mode)
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LIN master capability
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LIN slave mode
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SPI
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Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (f
following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
–
–
Transmission error detection with interrupt generation
Parity control
Emission: Generates 13-bit synch break frame
Reception: Detects 11-bit break frame
Autonomous header handling - one single interrupt per valid message header
Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 %
Synch delimiter checking
11-bit LIN synch break detection - break detection always active
Parity check on the LIN identifier field
LIN error management
Hot plugging support
Maximum speed: 10 Mbit/s (f
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave/master selection input pin
Address bit (MSB)
Idle line (interrupt)
Doc ID 14733 Rev 11
MASTER
/2) both for master and slave
CPU
/16) and capable of
Product overview
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