ML610Q435A-NNNTC03A7 Rohm Semiconductor, ML610Q435A-NNNTC03A7 Datasheet - Page 362

• Manufacturer Part Number: ML610Q435A-NNNTC03A7
• Description: MCU 8BIT 96K FLASH 144-LQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q435A-NNNTC03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

26.3.4
For amplification input, operate SA-ADC in the following procedure.
1. Before starting SA-ADC, start oscillation of the high-speed clock (HSCLK) and wait until the oscillator settles.
2. When HSCLK is within the range from 375KHz to 625kHz, set bit 1 (SACK) of the SA-ADC control register
3. Set the amplifier control register (AMPCON0) and SA-ADC mode register 0 (SADMOD0).
4. Set amplifier offset register (AMPOFFS) and amplifier gain register (AMPGAIN).
5. When bit 0 (SARUN) of SA-ADC control register 1 (SADCON1) is set to “1” after the amplifier control register
6. A/D conversion results are stored in the applicable SA-ADC result registers (SADRnL, SADRnH), and when A/D
7. A/D conversion is stopped when the A/D conversion terminates, and bit 0 (SARUN) of SA-ADC control register 1
Even if a channel is switched during A/D conversion, the channel that is selected at the start of A/D conversion is
maintained until an A/D conversion termination interrupt occurs.
Figure 26-4 shows the SA-ADC operation timing when channel 0 and channel 1 are selected.
* Amplifier settling time
The power-up time of the amplifier is 30 μs, the settling time of the amplifier after powered up is 54 μs, and the total
time is 84 μs.
Power-up of the amplifier means that amplifier control registers AMPEN1 and AMPEN0 are set from “0” and “0” to
“1” and “1” or to “1” and “0”, respectively.
Notes:
Since the supply current is increased while the amplifier is powered up, set amplifier control registers AMPEN1 and
AMPEN0 to “0” and “0” respectively to stop operating the amplifier if the amplifier is not used.
The A/D conversion time in 500 kHz RC oscillation mode is 46 μs.
(SADCON0) to “0” and when HSCLK is within the range from 1.5MHz to 4.2MHz, set it to “1”. Set bit 0 (SALP) to
“0”.
(AMPCON0 ) has been set and then the amplifier has been settled *, the SA-ADC circuit becomes active and
performs A/D conversion from the lower channel number that is selected in the SA-ADC mode register
(SADMOD0).
conversion terminates, the SA-ADC conversion termination interrupt is generated.
(SADCON1) is set to “0”.
A/D operation signal
Operation of the Successive Approximation A/D Converter in Amplification Input
AMPEN1, AMPEN0
A/D conversion
SADINT
SARUN
HSCLK
Figure 26-4 SA-ADC Operation Timing at Amplification Input
Amplifier settling time
84 μs@Max
Chapter 26 Successive Approximation Type A/D Converter
26 – 17
ML610Q435/ML610Q436 User’s Manual
26.86 μs@4.096MHz
Conversion time