XC3S1400AN-4FGG484C Xilinx Inc, XC3S1400AN-4FGG484C Datasheet - Page 78

• Manufacturer Part Number: XC3S1400AN-4FGG484C
• Description: IC FPGA SPARTAN-3AN 484FPGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S1400AN-4FGG484C

• Number Of Logic Elements/cells: 25344
• Number Of Labs/clbs: 2816
• Total Ram Bits: 589824
• Number Of I /o: 372
• Number Of Gates: 1400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8: Sector-Based Program/Erase Protection
Table 8-7: Sector Protection Register Read Command Sequence
78
MOSI
MISO
Pin
Command
Byte 1
0x32
Four-byte Command Sequence
Sector Protection Register Read
Sector Protection Register Limited to 10,000 Program/Erase Cycles
Byte 2
XX
The Sector Protection Register is limited to 10,000 erase/program cycles. If, as described
above, the FPGA application modifies the Sector Protection Register to temporarily
unprotect an individual sector or sectors, then the application must limit this practice to
10,000 cycles. Instead, use a combination of the techniques below.
•
•
To read the
command sequence. The FPGA application must perform the following actions using the
SPI_ACCESS design primitive.
•
•
•
•
Don’t Care
Byte 3
Temporarily unprotect individual sectors, but no more than 10,000 cycles
Use the
completely enable or disable the sector protection mechanism.
Drive CSB Low while CLK is High or on the rising edge of CLK.
On the falling edge of CLK, serially clock in the four-byte Sector Protection Register
Read command sequence shown in
each byte first. The last 3 bytes are dummy bytes.
After clocking in the last bit of the command sequence, read the Sector Protection
Register contents on the MISO pin.
♦
After clocking the last data bit to read the register, deassert the CSB pin High.
XX
The number of bytes depends on the Spartan-3AN FPGA, as highlighted in
Table 8-7
-
-
-
-
-
Sector Protection Register
Sector Protection Enable
The first data byte corresponds to Sector 0, the second data byte to Sector 1,
and so on.
The XC3S50AN FPGA provides four bytes.
The XC3S200AN and the XC3S400AN FPGAs each provide 8 bytes.
The XC3S700AN and XC3S1400AN FPGAs provide 16 bytes.
If the FPGA application reads more than required number of bytes from the
Sector Protection Register, any additional data provided on the MISO pin is
undefined.
Byte 4
XX
and
Sector 0
Sector Protection Register Value (byte locations corresponds to sector)
Table 8-3, page
Byte 5
XX
www.xilinx.com
XC3S50AN (4 bytes)
XC3S200AN, XC3S400AN (8 bytes)
Sector 1
Byte 6
XX
and
XC3S700AN, XC3S1400AN (16 bytes)
75.
contents, issue the Sector Protection Register Read
Table 8-7
Sector Protection Disable
Sector 2
Byte 7
Spartan-3AN FPGA In-System Flash User Guide
XX
on the MOSI pin, most-significant bit of
Sector 3
Byte 8
XX
UG333 (v2.1) January 15, 2009
...
...
...
Byte 12
Sector 7
commands to
XX
...
...
...
Sector 15
Byte 20
XX
R