XC3S1400AN-4FGG484C Xilinx Inc, XC3S1400AN-4FGG484C Datasheet - Page 45

• Manufacturer Part Number: XC3S1400AN-4FGG484C
• Description: IC FPGA SPARTAN-3AN 484FPGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S1400AN-4FGG484C

• Number Of Logic Elements/cells: 25344
• Number Of Labs/clbs: 2816
• Total Ram Bits: 589824
• Number Of I /o: 372
• Number Of Gates: 1400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
R
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The CSB signal must remain Low throughout the entire data transfer. A Low-to-High
transition on the CSB input completes the command.
The ISF memory first erases the selected memory page, then programs the page with the
data stored in the designated SRAM page buffer. The operation is internally self-timed and
completes in the Page Erase and Programming time, T
in the
During the command execution time, the
indicates whether the Page Erase and Programming operation is in progress or whether it
has completed.
Similarly, serially clock in a 24-bit starting page and byte address.
♦
♦
♦
♦
On the next falling CLK edge, serially supply the write data on the MOSI port.
♦
♦
♦
♦
To end the data transfer, drive CSB High on the falling edge of CLK.
Spartan-3AN FPGA data
The starting byte location can be anywhere within the selected SRAM page buffer,
as shown in
The page address must also be specified.
If using the default address scheme, see
If using power-of-2 addressing, see
Data is clocked in serially, most-significant bit first.
While CSB is Low, present new data on the MOSI pin on every subsequent falling
CLK edge. The ISF memory automatically increments the implied address
counter through the SRAM page buffer, as highlighted in
-
-
If the transaction reaches the end of a buffer, the ISF memory continues writing
back at the beginning of the buffer.
While it is possible to write less than a full page of data, be sure that the SRAM
page buffer contains valid data. The data from any unwritten buffer locations will
write the previous contents to the ISF memory page.
The first data byte written is stored in Byte Address + 0
The second data byte written is stored in Byte Address + 1, and so on.
Figure
www.xilinx.com
4-1.
sheet.
READY/BUSY
Table A-3, page 89
Table 2-2, page 19
PEP
, shown in
Page Program Through Buffer
bit (bit 7) of the
.
.
Figure
Table 4-4
4-1.
Status Register
and specified
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