XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 24

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
All Spartan-3AN FPGAs ship in two speed grades: -4 and
the higher performance -5. Switching characteristics in this
document are designated as Preview, Advance,
Preliminary, or Production, as shown in
category is defined as follows:
Preview: These specifications are based on estimates only
and should not be used for timing analysis.
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this
designation are considered relatively stable and
conservative, some under-reporting might still occur.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Production: These specifications are approved once
enough production silicon of a particular device family
member has been characterized to provide full correlation
between speed files and devices over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Typically, the slowest speed grades transition to Production
before faster speed grades.
Software Version Requirements
Production-quality systems must use FPGA designs
compiled using a speed file designated as PRODUCTION
status. FPGA designs using a less mature speed file
designation should only be used during system prototyping
or pre-production qualification. FPGA designs with speed
files designated as Preview, Advance, or Preliminary should
not be used in a production-quality system.
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the latest Xilinx®
ISE® software on the FPGA design to ensure that the
FPGA design incorporates the latest timing information and
software updates.
In some cases, a particular family member (and speed
grade) is released to Production at a different time than
when the speed file is released with the Production label.
Any labeling discrepancies are corrected in subsequent
speed file releases. See
considered to have the Production label.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan-3AN devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
DS557 (v4.1) April 1, 2011
Product Specification
Table 19
for devices that can be
Table
19. Each
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
• Sign Up for Alerts
https://secure.xilinx.com/webreg/register.do?group=myprofi
le&languageID=1
Timing parameters and their representative values are
selected for inclusion either because they are important as
general design requirements or they indicate fundamental
device performance characteristics. The Spartan-3AN
speed files (v1.41), part of the Xilinx Development Software,
are the original source for many but not all of the values.
The speed grade designations for these files are shown in
Table
data, use the values reported by the Xilinx static timing
analyzer (TRACE in the Xilinx development software) and
back-annotated to the simulation netlist.
Table 19: Spartan-3AN Family v1.41 Speed Grade
Designations
Table 20
speed files.
Table 20: Spartan-3AN Speed File Version History
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
Version
1.41
1.40
1.39
1.38
1.37
1.36
1.34
1.32
Device
19. For more complete, more precise, and worst-case
provides the recent history of the Spartan-3AN
ISE 10.1.03
ISE 10.1.02
ISE 9.2.03i
ISE 9.2.01i
ISE 9.1.03i Updated pin-to-pin timing.
ISE 9.1.01i Preview speed files for -4 speed grade.
Release
ISE 10.1
ISE 9.2i
ISE
Preview
Updated for Spartan-3A family. No
change to data for Spartan-3AN family.
Updated for Spartan-3A family. No
change to data for Spartan-3AN family.
Updated for Spartan-3A family. No
change to data for Spartan-3AN family.
Updated to Production. No change to
data.
Updated pin-to-pin setup and hold
times, TMDS output adjustment,
multiplier setup/hold times, and block
RAM clock width.
Added -5 speed grade, updated to
Advance.
Advance
Description
Preliminary
Production
-
-
-
-
-
4,
4,
4,
4,
4,
-
-
-
-
-
5
5
5
5
5
24