PCF8564ACX9/1,005 NXP Semiconductors, PCF8564ACX9/1,005 Datasheet - Page 22

• Manufacturer Part Number: PCF8564ACX9/1,005
• Description: IC RTC/CALENDAR I2C 9BUMP
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendar/Alarmr

Specifications of PCF8564ACX9/1,005

• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: Die
• Function: Serial Clock, Alarm, Calendar, Timer, Timer Interrupt
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1 V
• Mounting Style: SMD/SMT
• Rtc Bus Interface: I2C
• Supply Current: 1700 nA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 568-6640; PCF8564ACX9/1,005

NXP Semiconductors
PCF8564A
Product data sheet
Fig 14. System configuration
SCL
SDA
TRANSMITTER
9.4 Acknowledge
RECEIVER
MASTER
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
Acknowledgement on the I
Fig 15. Acknowledgment on the I
•
•
•
•
A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
by transmitter
data output
by receiver
data output
SCL from
master
RECEIVER
SLAVE
All information provided in this document is subject to legal disclaimers.
condition
Rev. 02 — 30 September 2010
START
S
2
C-bus is shown in
TRANSMITTER
RECEIVER
SLAVE
2
1
C-bus
Figure
2
TRANSMITTER
MASTER
15.
Real time clock and calendar
not acknowledge
acknowledge
8
TRANSMITTER
PCF8564A
RECEIVER
MASTER
acknowledgement
clock pulse for
© NXP B.V. 2010. All rights reserved.
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