PT7C4307WEX Pericom Semiconductor, PT7C4307WEX Datasheet - Page 9
![IC REAL TIME CLK/CALENDAR 8-SOIC](/photos/18/28/182870/8-soic_sml.jpg)
PT7C4307WEX
Manufacturer Part Number
PT7C4307WEX
Description
IC REAL TIME CLK/CALENDAR 8-SOIC
Manufacturer
Pericom Semiconductor
Type
Clock/Calendarr
Datasheet
1.PT7C4307WEX.pdf
(16 pages)
Specifications of PT7C4307WEX
Memory Size
56B
Time Format
Binary
Date Format
Binary
Interface
I²C, 2-Wire Serial
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PT7C4307WEXTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PT7C4307WEX
Manufacturer:
Pericom
Quantity:
4 200
Part Number:
PT7C4307WEX
Manufacturer:
PERICOM
Quantity:
20 000
Data Sheet
PT7C4307
2
Real-time Clock Module (I
C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
b) Data acknowledge response (ACK signal)
When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment
is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This
does not include instances where the master device intentionally does not generate an ACK signal.)
Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases
the SDA line and the receiver sets the SDA line to low (= acknowledge) level.
SCL from Master
8
9
2
1
SDA from transmitter
Release SDA
(sending side)
Low active
SDA from receiver
(receiving side)
ACK signal
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the
falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the
transmitter.
When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that
indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a
STOP condition from the Master.
PT0206(08/09)
Ver: 3
9