PT7C4307WEX Pericom Semiconductor, PT7C4307WEX Datasheet - Page 8
![IC REAL TIME CLK/CALENDAR 8-SOIC](/photos/18/28/182870/8-soic_sml.jpg)
PT7C4307WEX
Manufacturer Part Number
PT7C4307WEX
Description
IC REAL TIME CLK/CALENDAR 8-SOIC
Manufacturer
Pericom Semiconductor
Type
Clock/Calendarr
Datasheet
1.PT7C4307WEX.pdf
(16 pages)
Specifications of PT7C4307WEX
Memory Size
56B
Time Format
Binary
Date Format
Binary
Interface
I²C, 2-Wire Serial
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PT7C4307WEXTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PT7C4307WEX
Manufacturer:
Pericom
Quantity:
4 200
Part Number:
PT7C4307WEX
Manufacturer:
PERICOM
Quantity:
20 000
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Starting and Stopping I
1) START condition, repeated START condition, and STOP condition
which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the
START condition, the SDA level changes from high to low while SCL is at high level.
2) Data Transfers and Acknowledge Responses during I
a) Data transfers
Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount
(bytes) of data that are transferred between the START condition and STOP condition.
The address auto increment function operates during both write and read operations.
Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level.
The receiver (receiving side) captures data while the SCL line is at high level.
*Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART,
or STOP condition.
PT0206(08/09)
Fig 2. Starting and stopping on I
a) START condition
b) STOP condition
c) Repeated START condition (RESTART condition)
SDA level changes from low to high while SCL is at high level
SDA level changes from high to low while SCL is at high level
In some cases, the START condition occurs between a previous START condition and the next STOP condition, in
2
C Bus Communications
2
C bus
2
C-BUS Communication
8
Real-time Clock Module (I
Data Sheet
PT7C4307
2
C Bus)
Ver: 3