LIS331DLM STMicroelectronics, LIS331DLM Datasheet
LIS331DLM
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LIS331DLM Summary of contents
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... Thresholds and timing of interrupt generators are programmable by the end user on the fly. The LIS331DLM is available in small thin plastic Land Grid Array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C. ...
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... I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.1 5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.1 5.2.2 5.2.3 2/38 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Sleep to wake- I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Doc ID 15102 Rev 4 LIS331DLM ...
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... LIS331DLM 6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 WHO_AM_I (0Fh 7.2 CTRL_REG1 (20h 7.3 CTRL_REG2 (21h 7.4 CTRL_REG3 [Interrupt CTRL register] (22h 7.5 CTRL_REG4 (23h 7.6 CTRL_REG5 ( 7.7 HP_FILTER_RESET (25h 7.8 REFERENCE ( 7.9 STATUS_REG (27h 7.10 OUT_X (29 7.11 OUT_Y (2Bh 7.12 OUT_Z (2Dh ...
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... INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 38. Interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 39. INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 40. INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 41. INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 42. INT1_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 43. INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 44. INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 45. INT2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 46. INT2_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 47. Interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 48. INT2_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4/38 Doc ID 15102 Rev 4 LIS331DLM ...
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... LIS331DLM Table 49. INT2_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 50. INT2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 51. INT2_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 52. INT2_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 53. INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 54. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Doc ID 15102 Rev 4 List of tables 5/38 ...
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... Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. SPI slave timing diagram (2 Figure 4. I2C Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. LIS331DLM electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 8. Multiple bytes SPI read protocol (2 bytes example Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 10 ...
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... LIS331DLM 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram a SELF TEST 1.2 Pin description Figure 2. Pin connection X Y (TOP VIEW) DIRECTION OF THE DETECTABLE ACCELERATIONS X+ Y+ CHARGE AMPLIFIER Z+ A/D MUX CONVERTER TRIMMING REFERENCE CIRCUITS Z 1 Doc ID 15102 Rev 4 Block diagram and pin description ...
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... C less significant bit of the device address (SA0) SPI enable C/SPI mode selection (1: I INT 2 Inertial interrupt 2 Reserved Connect to GND INT 1 Inertial interrupt 1 GND 0 V supply GND 0 V supply Vdd Power supply Reserved Connect to Vdd GND 0 V supply Doc ID 15102 Rev 4 LIS331DLM Function 2 C mode; 0: SPI enabled) ...
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... LIS331DLM 2 Mechanical and electrical specifications 2.1 Mechanical characteristics Table 3. Mechanical characteristics @ Vdd = 2 °C unless otherwise noted Symbol Parameter FS Measurement range So Sensitivity Dres Device resolution Sensitivity change vs TCSo temperature Typical zero-g level offset TyOff (4),(5) accuracy Zero-g level change vs TCOff temperature Self-test ...
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... Test conditions (3) 0.8*Vdd_IO 0.9*Vdd_IO DR bit set bit set bit set bit set to 010 PM bit set to 011 PM bit set to 100 PM bit set to 101 PM bit set to 110 ODR = 100 Hz Doc ID 15102 Rev 4 LIS331DLM (1) (2) Min. Typ. Max. 2.16 2.5 3.6 1.71 Vdd+0.1 250 10 1 ...
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... LIS331DLM 2.3 Communication interface characteristics 2.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 5. SPI slave timing values Symbol tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time th(CS) CS hold time tsu(SI) SDI input setup time ...
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... Doc ID 15102 Rev 4 ( fast mode Min Max 100 0 400 1.3 0.6 100 0.01 0.9 ( 0.1C 300 300 20 + 0.1C 300 b 0.6 0.6 0.6 1.3 t su(SR) t w(SP:SR) t su(SP) LIS331DLM Unit KHz µs ns µs ns µs REPEATED START START STOP ...
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... LIS331DLM 2.4 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability ...
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... The “sleep to wake-up” function, in conjunction with low-power mode, allows to further reduce the system power consumption and develop new smart applications. LIS331DLM may be set in a low-power operating mode, characterized by lower date rates refreshments. In this way the device, even if sleeping, keep on sensing acceleration and generating interrupt requests. When the “ ...
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... The acceleration data may be accessed through an I device particularly suitable for direct interfacing with a microcontroller. The LIS331DLM features a data-ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device. ...
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... Application hints 4 Application hints Figure 5. LIS331DLM electrical connection Vdd Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Aluminum) should be placed as near as possible to the pin 14 of the device (common design practice) ...
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... The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the LIS331DLM. When the bus is free both the lines are high. 2 The I C interface is compliant with fast mode (400 kHz) I normal mode ...
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... If they match, the device considers itself addressed by the Master. The slave address (SAD) associated to the LIS331DLM is 000100xb. SDO/SA0 pad can be used to modify less significant bit of the device address. If SA0 pad is connected to voltage supply, LSb is ‘1’ (address 0001001b) else if SA0 pad is connected to ground, LSb value is ‘ ...
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... In the presented communication format MAK is Master Acknowledge and NMAK is no Master acknowledge. 5.2 SPI bus interface The LIS331DLM SPI is a bus slave. The SPI allows to write and read the registers of the device. The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. SAD + W ...
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... AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 RW MS AD5 AD4 AD3 AD2 AD1 AD0 Doc ID 15102 Rev 4 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 LIS331DLM ...
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... LIS331DLM The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. ...
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... DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 AD5 AD4 AD3 AD2 AD1 AD0 RW MS AD5 AD4 AD3 AD2 AD1 AD0 Doc ID 15102 Rev 4 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 LIS331DLM ...
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... LIS331DLM 6 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses: Table 15. Register address map Name Reserved (do not modify) WHO_AM_I Reserved (do not modify) CTRL_REG1 CTRL_REG2 CTRL_REG3 CTRL_REG4 CTRL_REG5 HP_FILTER_RESET REFERENCE STATUS_REG -- OUT_X -- OUT_Y ...
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... Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered-up. 24/38 Doc ID 15102 Rev 4 LIS331DLM ...
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... The registers address, made of 7 bits, is used to identify them and to write the data through serial interface. 7.1 WHO_AM_I (0Fh) Table 16. WHO_AM_I register 0 0 Device identification register. This register contains the device identifier that for LIS331DLM is set to 12h. 7.2 CTRL_REG1 (20h) Table 17. CTRL_REG1 register PM2 PM1 Table 18. CTRL_REG1 description Power mode selection ...
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... Normal mode 1 0 Low-power 1 1 Low-power 0 0 Low-power 0 1 Low-power 1 0 Low-power Output data rate [Hz] (1) DR0 ODR 100 0 400 HPM0 FDS Doc ID 15102 Rev 4 Output data rate [Hz] ODR - ODR 0 Low-pass filter cut-off frequency [Hz 292 HPen2 HPen1 HPCF1 Table 23) LIS331DLM LP HPCF0 ...
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... LIS331DLM Table 22. CTRL_REG2 description (continued) High pass filter enabled for Interrupt 1 source. Default value: 0 HPen1 (0: filter bypassed; 1: filter enabled) High pass filter cut-off frequency configuration. Default value: 00 HPCF1, HPCF0 (00: HPc=8; 01: HPc=16; 10: HPc=32; 11: HPc=64) BOOT bit is used to refresh the content of internal registers stored in the flash memory block ...
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... CTRL_REG4 (23h) Table 28. CTRL_REG4 register 0 0 28/38 LIR2 I2_CFG1 I2_CFG0 I1(2)_CFG0 0 1 Interrupt 1 source OR interrupt 2 source 0 1 FS1 FS0 STsign Doc ID 15102 Rev 4 LIS331DLM LIR1 I1_CFG1 I1_CFG0 INT 1(2) Pad Interrupt 1 (2) source Data ready Boot running 0 ST SIM ...
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... LIS331DLM Table 29. CTRL_REG4 description Full-scale selection. Default value: 00. FS1, FS0 (00: ±2 g; 01: ±4 g; 11: ±8 g) Self-test sign. Default value: 00. STsign (0: self-test plus; 1 self-test minus) Self-test enable. Default value (0: self-test disabled; 1: self-test enabled) SPI serial interface mode selection. Default value: 0. SIM (0: 4-wire interface; 1: 3-wire interface) 7 ...
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... Y-axis acceleration data. The value is expressed as two’s complement with 8 bit data representation right justified. 7.12 OUT_Z (2Dh) Z-axis acceleration data. The value is expressed as two’s complement with 8 bit data representation right justified. 30/38 YOR XOR ZYXDA Doc ID 15102 Rev 4 LIS331DLM ZDA YDA XDA ...
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... LIS331DLM 7.13 INT1_CFG (30h) Table 36. INT1_CFG register AOI 6D Table 37. INT1_CFG description AND/OR combination of Interrupt events. Default value: 0. AOI (See 6 direction detection function enable. Default value (See Enable interrupt generation on Z high event. Default value: 0 ZHIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z low event ...
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... INT1_SRC register if the latched option was chosen. 7.15 INT1_THS (32h) Table 41. INT1_THS register 0 THS6 Table 42. INT1_THS description THS6 - THS0 7.16 INT1_DURATION (33h) Table 43. INT1_DURATION register 0 D6 32/ THS5 THS4 Interrupt 1 threshold. Default value: 000 0000 D5 D4 Doc ID 15102 Rev THS3 THS2 THS1 LIS331DLM XL THS0 D0 ...
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... LIS331DLM Table 44. INT2_DURATION description bits set the minimum duration of the Interrupt 2 event to be recognized. Duration steps and maximum values depend on the ODR chosen. 7.17 INT2_CFG (34h) Table 45. INT2_CFG register AOI 6D Table 46. INT2_CFG description AND/OR combination of Interrupt events. Default value: 0. AOI (See table below) 6 direction detection function enable ...
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... INT2_SRC register if the latched option was chosen. 7.19 INT2_THS (36h) Table 50. INT2_THS register 0 THS6 Table 51. INT2_THS description THS6 - THS0 34/ THS5 THS4 Interrupt 1 threshold. Default value: 000 0000 Doc ID 15102 Rev 4 Interrupt mode AND combination of interrupt events 6 direction position recognition THS3 THS2 THS1 LIS331DLM XL THS0 ...
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... LIS331DLM 7.20 INT2_DURATION (37h) Table 52. INT2_DURATION register 0 D6 Table 53. INT2_DURATION description bits set the minimum duration of the interrupt 2 event to be recognized. Duration time steps and maximum values depend on the ODR chosen Duration value. Default value: 000 0000 Doc ID 15102 Rev 4 Register description ...
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... Doc ID 15102 Rev 4 LIS331DLM Outline and mechanical data LGA16 (3x3x1.0mm) Land Grid Array Package 7983231 ® ...
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... LIS331DLM 9 Revision history Table 54. Document revision history Date 16-Oct-2008 03-Nov-2008 21-Nov-2008 10-Jul-2009 Revision 1 Initial release Table , 15 have been updated Table 4 on page 10 3 Updated Table 4 on page Updated: page 13, Table 28 on page 4 Minor text changes to improve readability Doc ID 15102 Rev 4 Revision history ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 38/38 Please Read Carefully: © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 15102 Rev 4 LIS331DLM ...