LFE2M20E-5FN256C Lattice, LFE2M20E-5FN256C Datasheet - Page 112

• Manufacturer Part Number: LFE2M20E-5FN256C
• Description: FPGA - Field Programmable Gate Array 19K LUTs 140 I/O SERDES DSP -5
• Manufacturer: Lattice

Specifications of LFE2M20E-5FN256C

• Number Of Macrocells: 19000
• Maximum Operating Frequency: 311 MHz
• Number Of Programmable I/os: 140
• Data Ram Size: 1246208
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70
Single Ended User I/O
Differential Pair User I/O
Configuration
Non Configuration
VCC
VCCAUX
VCCPLL
VCCIO
GND, GND0 to GND7
NC
Single Ended/ Differential I/O
Pairs per Bank (including 
emulated with resistors)
True LVDS I/O Pairs per Bank
Pin Type
TAP Pins
Muxed Pins
Dedicated Pins (Non TAP)
Muxed Pins
Dedicated Pins
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0 (Top Edge)
Bank1 (Top Edge)
Bank2 (Right Edge)
Bank3 (Right Edge)
Bank4 (Bottom Edge)
Bank5 (Bottom Edge)
Bank6 (Left Edge)
Bank7 (Left Edge)
Bank8 (Right Edge)
4-9
484 fpBGA
50/25
46/23
38/19
22/11
46/23
46/23
40/20
37/18
14/7
339
169
14
68
16
16
60
10
5
7
3
4
4
4
4
4
4
4
4
4
2
0
0
0
9
5
0
0
8
0
LFE2-50
LatticeECP2/M Family Data Sheet
672 fpBGA
67/33
66/33
56/28
48/24
62/31
68/34
64/32
55/27
14/7
500
249
14
79
16
72
13
12
16
12
20
5
7
3
4
5
5
5
5
5
5
5
5
2
3
0
0
0
0
0
672 fpBGA
67/33
66/33
56/28
48/24
62/31
68/34
64/32
55/27
Pinout Information
14/7
500
249
14
79
20
16
72
13
12
16
12
5
7
3
2
5
5
5
5
5
5
5
5
2
5
0
0
0
0
0
LFE2-70
900 fpBGA
84/42
76/38
74/37
48/24
72/35
80/40
64/32
71/35
14/7
583
290
104
101
14
89
26
17
18
12
16
16
5
7
3
4
6
6
6
6
6
6
6
6
2
0
0
0
0
0