A54SX32A-PQG208 Actel, A54SX32A-PQG208 Datasheet - Page 12

• Manufacturer Part Number: A54SX32A-PQG208
• Description: FPGA - Field Programmable Gate Array 48K System Gates
• Manufacturer: Actel

Specifications of A54SX32A-PQG208

• Processor Series: A54SX32
• Core: IP Core
• Number Of Macrocells: 1800
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 249
• Delay Time: 4 ns to 8.4 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 32 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power-Up/Down and Hot Swapping
SX-A I/Os are configured to be hot-swappable, with the
exception of 3.3 V PCI. During power-up/down (or partial
up/down), all I/Os are tristated. V
have to be stable during power-up/down, and can be
powered up/down in any order. When the SX-A device is
plugged into an electrically active system, the device will
not degrade the reliability of or cause damage to the
host system. The device’s output pins are driven to a high
impedance state until normal chip operating conditions
Table 1-2 • I/O Features
Table 1-3 • I/O Characteristics for All I/O Configurations
Table 1-4 • Power-Up Time at which I/Os Become Active
1 -8
Function
Input Buffer Threshold Selections
Flexible Output Driver
Output Buffer
Power-Up
TTL, LVTTL, LVCMOS2
3.3 V PCI
5 V PCI
Supply Ramp Rate
Units
A54SX08A
A54SX16A
A54SX32A
A54SX72A
SX-A Family FPGAs
0.25 V/μs
μs
10
10
10
10
Hot Swappable
0.025 V/μs
CCA
Yes
Yes
No
100
100
100
μs
96
and V
Description
•
•
•
•
•
•
“Hot-Swap” Capability (3.3 V PCI is not hot swappable)
•
•
Selectable on an individual I/O basis
Individually selectable slew rate; high slew or low slew (The default is high slew rate).
The slew is only affected on the falling edge of an output. Rising edges of outputs are
not affected.
Individually selectable pull-ups and pull-downs during power-up (default is to power-up
in tristate)
Enables deterministic power-up of device
V
CCA
5 V: PCI, TTL
3.3 V: PCI, LVTTL
2.5 V: LVCMOS2 (commercial only)
5 V: PCI, TTL
3.3 V: PCI, LVTTL
2.5 V: LVCMOS2 (commercial only)
I/O on an unpowered device does not sink current
Can be used for “cold-sparing”
CCI
and V
5 V/ms
Yes. Only affects falling edges of outputs
Slew Rate Control
No. High slew rate only
No. High slew rate only
0.34
0.36
0.46
0.41
ms
do not
CCI
can be powered in any order
v5.3
2.5 V/ms
0.65
0.62
0.74
0.67
ms
are reached.
which the I/Os behave according to the user’s design for
an SX-A device at room temperature for various ramp-up
rates. The data reported assumes a linear ramp-up
profile to 2.5 V. For more information on power-up and
hot-swapping, refer to the application note,
and RT54SX-S Devices in Hot-Swap and Cold-Sparing
Applications.
0.5 V/ms
ms
2.7
2.5
2.8
2.6
Table 1-4
0.25 V/ms
summarizes the V
ms
5.4
4.7
5.2
5.0
Power-Up Resistor
Pull-up or pull-down
Pull-up or pull-down
Pull-up or pull-down
0.1 V/ms
12.9
11.0
12.1
12.1
ms
CCA
0.025 V/ms
Actel SX-A
voltage at
50.8
41.6
47.2
47.2
ms