LFE3-150EA-7FN672CTW Lattice, LFE3-150EA-7FN672CTW Datasheet - Page 54

• Manufacturer Part Number: LFE3-150EA-7FN672CTW
• Description: FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -7 Speed
• Manufacturer: Lattice

Specifications of LFE3-150EA-7FN672CTW

• Number Of Programmable I/os: 133 to 586
• Data Ram Size: 6.85 Mbits
• Delay Time: 37 ns
• Supply Voltage (max): 1.26 V
• Supply Current: 18 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-672
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Hot Socketing Specifications
Hot Socketing Requirements
ESD Performance
IDK_HS
IDK
1. V
2. Applicable to general purpose I/O pins in top I/O banks only.
3. I
4. LVCMOS and LVTTL only.
5. Applicable to general purpose I/O pins in left and right I/O banks only.
Input current per SERDES I/O pin when device is powered down and inputs
driven.
1. Assumes the device is powered down, all supplies grounded, both P and N inputs driven by CML driver with maximum allowed VCCOB
2. Each P and N input must have less than the specified maximum input current. For a 16-channel device, the total input current would be
Symbol
(1.575V), 8b10b data, internal AC coupling.
8mA*16 channels *2 input pins per channel = 256mA
DK
5
CC
is additive to I
, V
All pins
All pins except high-speed serial and XRES
High-speed serial inputs
1. The XRES pin on the TW device passes CDM testing at 250V.
2
CCAUX
Input or I/O Leakage Current
Input or I/O Leakage Current
and V
PU
CCIO
, I
PW
Parameter
should rise/fall monotonically.
Pin Group
or I
BH
.
Description
0 V
0  V
V
CCIO
1, 2
1, 3, 4
IN
IN
1
 V
 V
< V
Condition
IN
IH
CCIO
 V
(Max.)
ESD Stress
CCIO
3-2
HBM
CDM
CDM
+ 0.5V
DC and Switching Characteristics
Min.
Min.
—
—
—
—
LatticeECP3 Family Data Sheet
1000
Min.
500
400
Typ.
Typ.
18
—
—
—
Max.
Max.
+/-1
+/-1
Units
—
8
V
V
V
Units
Units
mA
mA
mA
mA