LFE3-150EA-7FN672CTW Lattice, LFE3-150EA-7FN672CTW Datasheet - Page 17

• Manufacturer Part Number: LFE3-150EA-7FN672CTW
• Description: FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -7 Speed
• Manufacturer: Lattice

Specifications of LFE3-150EA-7FN672CTW

• Number Of Programmable I/os: 133 to 586
• Data Ram Size: 6.85 Mbits
• Delay Time: 37 ns
• Supply Voltage (max): 1.26 V
• Supply Current: 18 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-672
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Secondary Clock/Control Sources
LatticeECP3 devices derive eight secondary clock sources (SC0 through SC7) from six dedicated clock input pads
and the rest from routing. Figure 2-14 shows the secondary clock sources. All eight secondary clock sources are
defined as inputs to a per-region mux SC0-SC7. SC0-SC3 are primary for control signals (CE and/or LSR), and
SC4-SC7 are for clock and high fanout data.
In an actual implementation, there is some overlap to maximize routability. In addition to SC0-SC3, SC7 is also an
input to the control signals (LSR or CE). SC0-SC2 are also inputs to clocks along with SC4-SC7. High fanout logic
signals (LUT inputs) will utilize the X2 and X0 switches where SC0-SC7 are inputs to X2 switches, and SC4-SC7
are inputs to X0 switches. Note that through X0 switches, SC4-SC7 can also access control signals CE/LSR.
Figure 2-14. Secondary Clock Sources
Secondary Clock/Control Routing
Global secondary clock is a secondary clock that is distributed to all regions. The purpose of the secondary clock
routing is to distribute the secondary clock sources to the secondary clock regions. Secondary clocks in the
LatticeECP3 devices are region-based resources. Certain EBR rows and special vertical routing channels bind the
secondary clock regions. This special vertical routing channel aligns with either the left edge of the center DSP
slice in the DSP row or the center of the DSP row. Figure 2-15 shows this special vertical routing channel and the
20 secondary clock regions for the LatticeECP3 family of devices. All devices in the LatticeECP3 family have eight
Clock Input
Clock Input
From Routing
From Routing
From Routing
From Routing
Note: Clock inputs can be configured in differential or single-ended mode.
Routing
Routing
From
From
Routing
Routing
From
From
Secondary Clock Sources
Clock
Input
2-14
Clock
Input
Routing
Routing
From
From
LatticeECP3 Family Data Sheet
Routing
Routing
From
From
From Routing
From Routing
From Routing
From Routing
Clock Input
Clock Input
Architecture