LFXP2-8E-5TN144C Lattice, LFXP2-8E-5TN144C Datasheet - Page 66

FPGA - Field Programmable Gate Array 8K LUTs 100I/O Inst- on DSP 1.2V -5 Spd

LFXP2-8E-5TN144C

Manufacturer Part Number
LFXP2-8E-5TN144C
Description
FPGA - Field Programmable Gate Array 8K LUTs 100I/O Inst- on DSP 1.2V -5 Spd
Manufacturer
Lattice
Series
LatticeXP2r
Datasheet

Specifications of LFXP2-8E-5TN144C

Number Of Macrocells
8000
Number Of Programmable I/os
100
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
TQFP-144
No. Of Logic Blocks
8000
No. Of Macrocells
4000
Family Type
LatticeXP2
No. Of Speed Grades
5
Total Ram Bits
221Kbit
No. Of I/o's
100
Clock Management
PLL
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFXP2-8E-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LFXP2-8E-5TN144C
Manufacturer:
LATTICE
Quantity:
1 000
Part Number:
LFXP2-8E-5TN144C
Manufacturer:
LATTICE
Quantity:
20 000
Lattice Semiconductor
EBR Timing Diagrams
Figure 3-6. Read/Write Mode (Normal)
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
Figure 3-7. Read/Write Mode with Input and Output Registers
CLKA
DOA (Regs)
WEA
DOA
CSA
ADA
DIA
CLKA
WEA
ADA
CSA
DIA
t
SU
A0
D0
t
t
H
SU
A0
D0
t
H
Invalid Data
Mem(n) data from previous read
A1
D1
A1
D1
3-22
output is only updated during a read cycle
A0
t
A0
CO_EBR
t
COO_EBR
DC and Switching Characteristics
D0
A1
A1
t
CO_EBR
LatticeXP2 Family Data Sheet
D0
D1
A0
A0
t
CO_EBR
t
COO_EBR
D1
D0

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