AFS250-PQG208 Actel, AFS250-PQG208 Datasheet - Page 268

FPGA - Field Programmable Gate Array 250K System Gates

AFS250-PQG208

Manufacturer Part Number
AFS250-PQG208
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet

Specifications of AFS250-PQG208

Processor Series
AFS250
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
93
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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DC and Power Characteristics
Table 3-12 • Summary of I/O Input Buffer Power (per pin)—Default I/O Software Settings
3- 18
Applicable to Pro I/O Banks
Single-Ended
3.3 V LVTTL/LVCMOS
3.3 V LVTTL/LVCMOS – Schmitt trigger
2.5 V LVCMOS
2.5 V LVCMOS – Schmitt trigger
1.8 V LVCMOS
1.8 V LVCMOS – Schmitt trigger
1.5 V LVCMOS (JESD8-11)
1.5 V LVCMOS (JESD8-11) – Schmitt trigger
3.3 V PCI
3.3 V PCI – Schmitt trigger
3.3 V PCI-X
3.3 V PCI-X – Schmitt trigger
Voltage-Referenced
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Differential
LVDS
LVPECL
Notes:
1. P
2. P
AC9
DC7
is the total dynamic power measured on VCC and VCCI.
is the static power (where applicable) measured on VCCI.
Power per I/O Pin
VCCI (V)
3.3
2.5
3.3
2.5
1.5
1.5
2.5
2.5
3.3
3.3
2.5
3.3
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
3.3
3.3
3.3
3.3
R e visio n 1
Static Power
P
DC7
2.90
2.13
2.81
2.57
0.17
0.17
1.38
1.38
3.21
3.21
2.26
5.71
(mW)
1
Dynamic Power
P
AC9
(µW/MHz)
17.39
25.51
18.82
20.12
18.82
20.12
5.76
7.16
2.72
2.80
2.08
2.00
2.03
2.03
4.48
4.48
9.26
9.26
1.50
2.17
8.23
4.78
4.14
3.71
2

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