APA600-PQG208 Actel, APA600-PQG208 Datasheet - Page 77

• Manufacturer Part Number: APA600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of APA600-PQG208

• Processor Series: APA600
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 454
• Data Ram Size: 129024
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Asynchronous FIFO Read
Note: The plot shows the normal operation status.
Figure 2-40 • Asynchronous FIFO Read
Table 2-63 • T
Symbol t
ERDH, FRDH,
THRDH
ERDA
FRDA
ORDA
ORDH
RDCYC
RDWRS
RDH
RDL
RPRDA
RPRDH
THRDA
Notes:
1. At fast cycles, ERDA and FRDA = MAX (7.5 ns – RDL), 3.0 ns.
2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns – WRL), 3.0 ns.
xxx
T
J
J
= 0°C to 110°C; V
= –55°C to 150°C, V
Old EMPTY, FULL, EQTH, & GETH valid hold
time from RB ↑
New DO access from RB ↓
WB ↑, clearing EMPTY, setup to
RB high phase
Old RPE valid from RB ↓
New EMPTY access from RB ↑
FULL↓ access from RB ↑
Old DO valid from RB ↓
Read cycle time
RB ↓
RB low phase
New RPE access from RB ↓
EQTH or GETH access from RB↑
RB = (RDB+RBLKB)
Description
EQTH, GETH
DD
DD
= 2.3 V to 2.7 V for Commercial/Industrial
EMPTY
RDATA
t RDWRS
FULL
= 2.3 V to 2.7 V for Military/MIL-STD-883
RPE
WB
t RPRDH
t ORDH
t ORDA
t RPRDA
t RPRDA
Cycle Start
t RDL
t RDL
Min.
3.0
3.0
3.0
7.5
7.5
3.0
3.0
9.5
4.5
v5.9
1
1
2
t RDCYC
Max.
0.5
3.0
1.0
4.0
t THRDH
t THRDA
t RDH
t RDH
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Empty inhibits read)
Empty/full/thresh are invalid from the end
of hold until the new access is complete
Enabling the read operation
Inhibiting the read operation
Inactive
Active
t ERDH , t FRDH
t ERDA , t FRDA
ProASIC
PLUS
Notes
Flash Family FPGAs
2-67