A3PN030-ZQNG68 Actel, A3PN030-ZQNG68 Datasheet - Page 59
![FPGA - Field Programmable Gate Array 30K System Gates ProASIC3 nano](/photos/16/15/161506/qfn-68_sml.jpg)
A3PN030-ZQNG68
Manufacturer Part Number
A3PN030-ZQNG68
Description
FPGA - Field Programmable Gate Array 30K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet
1.A3PN030-ZVQG100.pdf
(106 pages)
Specifications of A3PN030-ZQNG68
Processor Series
A3PN030
Core
IP Core
Number Of Macrocells
256
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
49
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
30 K
Package / Case
QFN-68
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3PN030-ZQNG68I
Manufacturer:
ACT
Quantity:
5
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DDR Module Specifications
Input DDR Module
Figure 2-15 • Input DDR Timing Model
Table 2-61 • Parameter Definitions
Parameter Name
t
t
t
t
t
t
t
t
CLK
Data
DDRICLKQ1
DDRICLKQ2
DDRISUD
DDRIHD
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
CLR
INBUF
CLKBUF
INBUF
Clock-to-Out Out_QR
Clock-to-Out Out_QF
Data Setup Time of DDR input
Data Hold Time of DDR input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
Clear Recovery
A
B
C
Parameter Definition
R e v i s i o n 8
Input DDR
DDR_IN
FF1
FF2
Measuring Nodes (from, to)
ProASIC3 nano Flash FPGAs
D
E
B, D
C, D
C, E
C, B
C, B
B, E
A, B
A, B
Out_QF
(to core)
Out_QR
(to core)
2- 45
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