A3PN030-ZQNG68 Actel, A3PN030-ZQNG68 Datasheet - Page 26
![FPGA - Field Programmable Gate Array 30K System Gates ProASIC3 nano](/photos/16/15/161506/qfn-68_sml.jpg)
A3PN030-ZQNG68
Manufacturer Part Number
A3PN030-ZQNG68
Description
FPGA - Field Programmable Gate Array 30K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet
1.A3PN030-ZVQG100.pdf
(106 pages)
Specifications of A3PN030-ZQNG68
Processor Series
A3PN030
Core
IP Core
Number Of Macrocells
256
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
49
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
30 K
Package / Case
QFN-68
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3PN030-ZQNG68I
Manufacturer:
ACT
Quantity:
5
ProASIC3 nano DC and Switching Characteristics
User I/O Characteristics
Figure 2-2 • Timing Model
2- 12
Input LVCMOS 2.5 V
LVCMOS 1.5 V
t
PY
= 0.84 ns
Timing Model
Clock
Input LVTTL
Operating Conditions: –2 Speed, Commercial Temperature Range (T
VCC = 1.425 V, with Default Loading at 10 pF
t
PY
(Non-Registered)
(Registered)
= 1.04 ns
t
I/O Module
I/O Module
t
t
PY
ICLKQ
ISUD
= 1.14 ns
= 0.26 ns
= 0.24 ns
D
Q
Register Cell
t
t
CLKQ
SUD
D
= 0.43 ns
= 0.55 ns
Combinational Cell
Q
Combinational Cell
t
PD
Combinational Cell
t
PD
Clock
Input LVTTL
t
PY
= 0.87 ns
t
= 0.56 ns
PD
= 0.84 ns
= 0.47 ns
Combinational Cell
Combinational Cell
Y
Y
t
PD
t
PD
Y
R e visio n 8
= 0.51 ns
= 0.47 ns
Register Cell
Combinational Cell
t
t
CLKQ
SUD
t
D
PD
Y
Y
= 0.43 ns
(Non-Registered)
= 0.55 ns
= 0.49 ns
I/O Module
t
Q
DP
Clock
t
Input LVTTL
PY
= 2.87 ns
(Non-Registered)
(Non-Registered)
t
t
DP
I/O Module
DP
I/O Module
= 0.84 ns
Y
= 3.02 ns
= 2.21 ns
(Non-Registered)
t
I/O Module
DP
LVTTL Output drive strength = 4 mA
= 2.25 ns
D
t
t
OCLKQ
OSUD
(Registered)
I/O Module
LVTTL Output drive strength = 8 mA
LVCMOS 1.5 V Output drive strength = 2 mA
High slew rate
Q
= 0.31 ns
= 0.59 ns
t
DP
High slew rate
J
= 2.21 ns
LVCMOS 2.5V Output Drive
Strength = 8 mA High Slew Rate
= 70°C), Worst Case
High slew rate
LVTTL 3.3 V Output drive
strength = 8 mA High slew rate