A42MX16-TQG176 Actel, A42MX16-TQG176 Datasheet - Page 16
![no-image](/images/manufacturer_photos/0/0/8/actel_sml.jpg)
A42MX16-TQG176
Manufacturer Part Number
A42MX16-TQG176
Description
FPGA - Field Programmable Gate Array 24K System Gates
Manufacturer
Actel
Datasheet
1.A40MX04-PLG44.pdf
(124 pages)
Specifications of A42MX16-TQG176
Processor Series
A42MX16
Core
IP Core
Number Of Macrocells
608
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
140
Delay Time
5.6 ns
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
3 V
Number Of Gates
24 K
Package / Case
TQFP-176
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A42MX16-TQG176
Manufacturer:
Actel
Quantity:
135
Company:
Part Number:
A42MX16-TQG176
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A42MX16-TQG176
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Company:
Part Number:
A42MX16-TQG176A
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A42MX16-TQG176I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Figure 1-13 • Silicon Explorer II Setup with 42MX
Table 2 •
Design Consideration
It is recommended to use a series 70Ω termination
resistor on every probe connector (SDI, SDO, MODE,
DCLK, PRA and PRB). The 70Ω series termination is used
to prevent data transmission corruption during probing
and reading back the checksum.
IEEE Standard 1149.1 Boundary Scan Test
(BST) Circuitry
42MX24 and 42MX36 devices are compatible with IEEE
Standard 1149.1 (informally known as Joint Testing
Action Group Standard or JTAG), which defines a set of
hardware architecture and mechanisms for cost-effective
board-level testing. The basic MX boundary-scan logic
circuit is composed of the TAP (test access port), TAP
controller, test data registers and instruction register
(Figure 1-14 on page
mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/
PRELOAD and BYPASS) and some optional instructions.
Table 3 on page 1-11
JTAG testing, while
test instructions supported by these MX devices.
1 -1 0
Security Fuse(s)
Programmed
No
No
Yes
Notes:
1. Avoid using SDI, SDO, DCLK, PRA and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the <zBlue>“Pin Descriptions” section
40MX and 42MX FPGA Families
signals will not pass through these pins and may cause contention.
on page 77 for information on unused I/O pins.
Device Configuration Options for Probe Capability
Table 4 on page 1-11
describes the ports that control
1-11). This circuit supports all
Serial Connection
to Windows PC
16 Logic Analyzer Channels
MODE
HIGH
LOW
describes the
–
Explorer II
Silicon
v6.1
PRB
Each test section is accessed through the TAP, which has
four associated pins: TCK (test clock input), TDI and TDO
(test data input and output), and TMS (test mode
selector).
and '0's represent the values that must be present at TMS
at a rising edge of TCK for the given state transition to
occur. IR and DR indicate that the instruction register or
the data register is operating in that state.
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest
of the test logic architecture. On power-up, the TAP
controller enters the Test-Logic-Reset state. To guarantee
a reset of the controller from any of the possible states,
TMS must remain high for five TCK cycles.
42MX24 and 42MX36 devices support three types of test
data
boundary scan. The bypass register is selected when no
other register needs to be accessed in a device. This
speeds up test data transfer to other devices in a test
data path. The 32-bit device identification register is a
shift register with four fields (lowest significant byte
(LSB), ID number, part number and version). The
boundary-scan register observes and controls the state of
each I/O pin.
The TAP controller is a four-bit state machine. The '1's
Probe Circuit Outputs
PRA
Probe Circuit Secured
MODE
DCLK
SDO
SDI
registers:
PRA, PRB
User I/Os
2
1
bypass,
42MX
device
Probe Circuit Secured
SDI, SDO, DCLK
Probe Circuit Inputs
identification,
User I/Os
2
1
and