AGL400V5-FGG484 Actel, AGL400V5-FGG484 Datasheet - Page 145
![FPGA - Field Programmable Gate Array 400K System Gates](/photos/16/15/161507/fgba-484_sml.jpg)
AGL400V5-FGG484
Manufacturer Part Number
AGL400V5-FGG484
Description
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL400V5-FGG484
Processor Series
AGL400
Core
IP Core
Number Of Logic Blocks
12
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
194
Data Ram Size
54 Kbit
Supply Voltage (max)
1.5 V
Supply Current
27 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
400 K
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL400V5-FGG484
Manufacturer:
Actel
Quantity:
135
Company:
Part Number:
AGL400V5-FGG484
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AGL400V5-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Table 2-194 • FIFO
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
ENS
ENH
BKS
BKH
DS
DH
CKQ1
CKQ2
RCKEF
WCKFF
CKAF
RSTFG
RSTAF
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
For specific junction temperature and voltage supply levels, refer to
Timing Characteristics
1.5 V DC Core Voltage
Worst Commercial-Case Conditions: T
REN_B, WEN_B Setup Time
REN_B, WEN_B Hold Time
BLK_B Setup Time
BLK_B Hold Time
Input Data (DI) Setup Time
Input Data (DI) Hold Time
Clock High to New Data Valid on DO (flow-through)
Clock High to New Data Valid on DO (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET_B Low to Empty/Full Flag Valid
RESET_B Low to Almost Empty/Full Flag Valid
RESET_B Low to Data Out Low on DO (flow-through)
RESET_B Low to Data Out Low on DO (pipelined)
RESET_B Removal
RESET_B Recovery
RESET_B Minimum Pulse Width
Clock Cycle Time
Maximum Frequency for FIFO
Description
J
= 70°C, VCC = 1.425 V
R ev i si o n 1 8
Table 2-6 on page 2-7
IGLOO Low Power Flash FPGAs
for derating values.
12.85
12.72
1.99
0.16
0.30
0.00
0.76
0.25
3.33
1.80
3.53
3.35
3.48
2.02
2.02
0.61
3.21
0.68
6.24
Std.
160
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 131
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