LFE2M20SE-5FN484C Lattice, LFE2M20SE-5FN484C Datasheet - Page 125

• Manufacturer Part Number: LFE2M20SE-5FN484C
• Description: FPGA - Field Programmable Gate Array 19K LUTs 304 I/O S-Ser SERDES DSP -5
• Manufacturer: Lattice

Specifications of LFE2M20SE-5FN484C

• Number Of Macrocells: 19000
• Maximum Operating Frequency: 311 MHz
• Number Of Programmable I/os: 304
• Data Ram Size: 1246208
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP
Number
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
1
2
3
4
5
6
7
8
9
LLM0_PLLCAP
Function
Pin/Pad
VCCAUX
VCCAUX
VCCIO7
VCCIO6
VCCIO5
PL12A
PL13A
PL13B
PL15A
PL16A
PL16B
PL18A
PL18B
PL20A
PL20B
PL22A
PL12B
PL15B
VCCJ
PL2A
PL2B
PL4A
PL4B
PL6A
PL6B
PL8A
PL8B
PB2A
PB2B
PB4A
PB4B
PB6A
PB6B
GND
GND
GND
VCC
VCC
VCC
TCK
TDO
TMS
TDI
NC
Bank
LFE2-6E/SE
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
LLM0_GPLLC_IN_A**
LLM0_GPLLT_IN_A**
LLM0_GDLLC_FB_A
LLM0_GDLLT_FB_A
PCLKC7_0/LDQ10
PCLKT7_0/LDQ10
Dual Function
VREF2_5/BDQ6
VREF1_5/BDQ6
PCLKT6_0
PCLKC6_0
VREF2_7
VREF1_7
VREF2_6
VREF1_6
BDQS6
LDQ10
LDQ10
LDQ10
LDQ10
LDQ10
LDQ10
BDQ6
BDQ6
BDQ6
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
4-22
C
C
C
C
C
C
T
T
T
T
T
T
LLM0_PLLCAP
Function
Pin/Pad
VCCAUX
VCCAUX
VCCIO7
VCCIO6
VCCIO5
PL20A
PB12A
PB12B
PB16A
PL12A
PL12B
PL13A
PL13B
PL15A
PL15B
PL16A
PL16B
PL18A
PL18B
PL20B
PL22A
VCCJ
PL2A
PL2B
PL4A
PL4B
PL6A
PL6B
PL8A
PL8B
PB2A
PB2B
PB6A
PB6B
GND
GND
GND
VCC
VCC
VCC
TCK
TDO
TMS
TDI
LatticeECP2/M Family Data Sheet
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
LFE2-12E/12SE
LLM0_GPLLC_IN_A**
LLM0_GPLLT_IN_A**
LLM0_GDLLC_FB_A
LLM0_GDLLT_FB_A
PCLKT7_0/LDQ10
PCLKC7_0/LDQ10
VREF2_5/BDQ6
VREF1_5/BDQ6
PCLKC6_0
PCLKT6_0
Function
VREF2_7
VREF1_7
VREF2_6
VREF1_6
BDQS6
BDQ15
BDQ15
BDQ15
LDQ10
LDQ10
LDQ10
LDQ10
LDQ10
LDQ10
BDQ6
Dual
Pinout Information
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
T
T
T
T
T
T
T