LFE2M20SE-5FN484C Lattice, LFE2M20SE-5FN484C Datasheet - Page 114

• Manufacturer Part Number: LFE2M20SE-5FN484C
• Description: FPGA - Field Programmable Gate Array 19K LUTs 304 I/O S-Ser SERDES DSP -5
• Manufacturer: Lattice

Specifications of LFE2M20SE-5FN484C

• Number Of Macrocells: 19000
• Maximum Operating Frequency: 311 MHz
• Number Of Programmable I/os: 304
• Data Ram Size: 1246208
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35
Lattice Semiconductor
Single Ended User I/O
Differential Pair User I/O
Configuration
Non Configuration
VCC
VCCAUX
VCCPLL
VCCIO
GND, GND0 to GND7
NC
Single Ended/ Differential I/O
Pairs per Bank (including
emulated with resistors)
True LVDS I/O Pairs per Bank
Pin Type
TAP Pins
Muxed Pins
Dedicated Pins (Non TAP)
Muxed Pins
Dedicated Pins
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0 (Top Edge)
Bank1 (Top Edge)
Bank2 (Right Edge)
Bank3 (Right Edge)
Bank4 (Bottom Edge)
Bank5 (Bottom Edge)
Bank6 (Left Edge)
Bank7 (Left Edge)
Bank8 (Right Edge)
256 fpBGA 484 fpBGA 256 fpBGA 484 fpBGA 672 fpBGA
4-11
32/16
20/10
28/14
14/7
16/8
16/8
14/7
140
0/0
0/0
70
14
64
22
17
5
7
3
6
4
1
1
1
2
2
2
2
2
2
1
0
0
3
4
0
0
4
7
0
LFE2M20
36/18
30/15
36/18
62/31
28/14
40/20
40/20
18/9
14/7
304
152
14
84
16
57
11
10
10
5
7
3
8
4
4
3
4
4
4
4
4
4
2
0
0
7
9
0
0
0
LatticeECP2/M Family Data Sheet
32/16
20/10
28/14
14/7
16/8
16/8
14/7
140
0/0
0/0
70
14
60
22
17
4
7
5
7
3
6
4
1
1
1
2
2
2
2
2
2
1
0
0
3
4
0
0
0
Pinout Information
LFE2M35
36/18
30/15
36/18
62/31
28/14
39/19
40/20
18/9
14/7
303
151
14
84
16
57
12
10
10
5
7
3
8
4
4
3
4
4
4
4
4
4
2
0
0
7
9
0
0
0
63/31
50/25
43/21
50/21
60/30
52/25
60/30
18/9
14/7
410
199
14
89
29
17
80
37
12
11
14
15
5
7
3
8
5
4
5
5
4
5
5
5
2
0
0
0
0
0