LFXP6C-3QN208C Lattice, LFXP6C-3QN208C Datasheet - Page 94

• Manufacturer Part Number: LFXP6C-3QN208C
• Description: FPGA - Field Programmable Gate Array 5.8K LUTS 142 I/O
• Manufacturer: Lattice

Specifications of LFXP6C-3QN208C

• Number Of Macrocells: 6000
• Maximum Operating Frequency: 320 MHz
• Number Of Programmable I/os: 142
• Data Ram Size: 73728
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)
Number
Ball
AA2
AA1
AB2
AA3
AB3
AA4
AB4
AA5
AB5
AA6
AB6
W1
W2
W5
W3
W4
W6
W7
W8
W9
U1
U2
R3
R4
U4
U3
T2
V1
V2
P3
P4
Y1
T3
T4
V4
V3
Y2
Y3
Y4
Y5
Y6
Y9
-
-
-
-
-
-
-
SLEEPN
Function
GNDIO6
GNDIO6
GNDIO6
GNDIO5
GNDIO5
GNDIO5
GNDIO5
PL25A
PL25B
PL26A
PL26B
PL28A
PL28B
PL29A
PL29B
PL30A
PL30B
PL31A
PL32B
PL33A
PL33B
PL34A
PL34B
PL35A
PL35B
PB10A
PB10B
PB11A
INITN
PB2A
PB3A
PB3B
PB4A
PB4B
PB5A
PB5B
PB6A
PB6B
PB7A
PB7B
PB8A
PB9B
TOE
Ball
-
-
-
-
-
-
2
1
/
Bank Diff.
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
-
-
-
-
-
LFXP10
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
LLM0_PLLC_FB_A
LLM0_PLLT_FB_A
LLM0_PLLC_IN_A
LLM0_PLLT_IN_A
Dual Function
VREF2_6
VREF1_5
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SLEEPN
Function
GNDIO6
GNDIO6
GNDIO6
GNDIO5
GNDIO5
GNDIO5
GNDIO5
PB15A
PL29A
PL29B
PL30A
PL30B
PL32A
PL32B
PL33A
PL33B
PL34A
PL34B
PL35A
PL36B
PL37A
PL37B
PL38A
PL38B
PL39A
PL39B
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
PB14B
PB15B
PB16A
INITN
PB3B
PB4A
PB4B
PB5A
PB6B
PB7A
PB7B
PB8A
PB8B
PB9A
PB9B
TOE
Ball
2
1
/
Bank Diff.
4-35
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
LFXP15
C
C
C
C
C
T
T
T
T
T
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
LLM0_PLLC_FB_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLT_IN_A
Dual Function
VREF2_6
VREF1_5
DQS
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LatticeXP Family Data Sheet
SLEEPN
Function
GNDIO6
GNDIO6
GNDIO6
GNDIO5
GNDIO5
GNDIO5
GNDIO5
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
PB18B
PB19A
PB19B
PB20A
PL33A
PL33B
PL34A
PL34B
PL36A
PL36B
PL37A
PL37B
PL38A
PL38B
PL39A
PL40B
PL41A
PL41B
PL42A
PL42B
PL43A
PL43B
INITN
TOE
PB7B
PB8A
PB8B
PB9A
Ball
2
1
/
Bank Diff.
Pinout Information
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
LFXP20
C
C
C
C
C
T
T
T
T
T
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
LLM0_PLLC_FB_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLT_IN_A
Dual Function
VREF2_6
VREF1_5
DQS
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-