LFXP6C-3QN208C Lattice, LFXP6C-3QN208C Datasheet - Page 81

• Manufacturer Part Number: LFXP6C-3QN208C
• Description: FPGA - Field Programmable Gate Array 5.8K LUTS 142 I/O
• Manufacturer: Lattice

Specifications of LFXP6C-3QN208C

• Number Of Macrocells: 6000
• Maximum Operating Frequency: 320 MHz
• Number Of Programmable I/os: 142
• Data Ram Size: 73728
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.)
Number
M16
Ball
N16
K14
K15
K12
K13
K16
H16
H13
H12
H15
H14
G15
G14
G16
G13
G12
B16
C16
E15
E14
D15
C15
L15
L14
L12
L16
F16
F13
F15
F14
J15
J14
J13
J12
J16
-
-
-
-
-
-
Function
GNDIO3
GNDIO3
GNDIO2
GNDIO2
GNDIO2
GNDIO2
GNDP1
VCCP1
PR21B
PR21A
PR17B
PR20B
PR20A
PR19B
PR19A
PR17A
PR22A
PR18B
PR18A
PR16B
PR16A
PR12B
PR12A
PR13B
PR13A
PR11B
PR11A
PR14A
PR2B
PR6B
PR8B
PR8A
PR2A
PR9B
PR9A
PR7B
PR7A
PR5A
PR4B
PR4A
PR3B
PR3A
Ball
Bank Differential
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
LFXP6
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
C
C
C
C
C
T
T
T
T
T
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
RUM0_PLLC_FB_A
RUM0_PLLT_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
PCLKC2_0
PCLKT2_0
VREF2_3
VREF1_2
VREF2_2
Function
Dual
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4-22
Function
GNDIO3
GNDIO3
GNDIO2
GNDIO2
GNDIO2
GNDIO2
GNDP1
VCCP1
PR28B
PR28A
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
PR22A
PR21B
PR21A
PR19B
PR19A
PR17B
PR17A
PR16B
PR16A
PR15B
PR14A
PR13B
PR13A
PR12B
PR12A
PR11B
PR8B
PR8A
PR7B
PR7A
PR6B
PR5A
PR4B
PR4A
PR3B
PR3A
Ball
Bank Differential
LatticeXP Family Data Sheet
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
LFXP10
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
C
C
C
C
C
T
T
T
T
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pinout Information
RUM0_PLLC_FB_A
RUM0_PLLT_FB_A
RUM0_PLLC_IN_A
RLM0_PLLC_IN_A
RUM0_PLLT_IN_A
RLM0_PLLT_IN_A
PCLKC2_0
PCLKT2_0
VREF2_3
VREF1_2
VREF2_2
Function
Dual
DQS
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-