A3P1000-FGG484 Actel, A3P1000-FGG484 Datasheet - Page 67
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A3P1000-FGG484
Manufacturer Part Number
A3P1000-FGG484
Description
FPGA - Field Programmable Gate Array 1M System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P1000-FGG484
Processor Series
A3P1000
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
300
Data Ram Size
147456
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
1000 K
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P1000-FGG484
Manufacturer:
FUJITSU
Quantity:
1 000
Company:
Part Number:
A3P1000-FGG484
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P1000-FGG484
Manufacturer:
ACTEL
Quantity:
20 000
Company:
Part Number:
A3P1000-FGG484I
Manufacturer:
ATMEL
Quantity:
101
Company:
Part Number:
A3P1000-FGG484I
Manufacturer:
Microsemi SoC
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Part Number:
A3P1000-FGG484I
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MICROSEMI/美高森美
Quantity:
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Company:
Part Number:
A3P1000-FGG484T
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-66 • Minimum and Maximum DC Input and Output Levels
Table 2-67 • Minimum and Maximum DC Input and Output Levels
1.8 V
LVCMOS
Drive
Strength
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
1.8 V
LVCMOS
Drive
Strength
2 mA
4 mA
6 mA
8 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
larger when operating outside recommended ranges
larger when operating outside recommended ranges
IL
IH
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <V CCI. Input current is
Min.
–0.3
Applicable to Advanced I/O Banks
–0.3
–0.3
–0.3
Applicable to Standard Plus I/O I/O Banks
–0.3
–0.3
Min.
–0.3
–0.3
–0.3
–0.3
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
V
V
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
VIL
VIL
Max.,
Max.
V
V
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * V
Min.
Min.
V
V
VIH
VIH
CCI
Max.
Max.
3.6
3.6
3.6
3.6
1.9
1.9
1.9
1.9
1.9
1.9
V
V
R e v i s i o n 9
Max.
VOL
0.45
0.45
0.45
0.45
Max.
VOL
0.45
0.45
0.45
0.45
0.45
0.45
V
V
VCCI – 0.45
VCCI – 0.45
VCCI – 0.45
VCCI – 0.45
VCCI – 0.45
VCCI – 0.45
VCCI – 0.45
VCCI – 0.45
VCCI – 0.45 12 12
VCCI – 0.45 16 16
VOH
Min.
VOH
Min.
V
V
mA mA
mA mA
I
I
OL
8
OL
2
4
6
6
2
4
8
I
I
OH
6
OH
4
8
2
2
4
6
8
ProASIC3 Flash Family FPGAs
Max.
Max.
mA
mA
I
I
OSL
OSL
22
44
44
11
22
44
51
74
74
11
3
3
Max.
I
mA
OSH
Max.
I
mA
17
35
35
OSH
9
35
17
45
91
91
9
3
3
µA
I
µA
10
10
10
10
IL
I
IL
10 10
10 10
10 10
10 10
10 10
10 10
1
4
1
4
µA
µA
I
I
2- 53
10
10
10
10
IH
IH
2
2
4
4