APA300-FGG256 Actel, APA300-FGG256 Datasheet - Page 18

• Manufacturer Part Number: APA300-FGG256
• Description: FPGA - Field Programmable Gate Array 300K System Gates
• Manufacturer: Actel

Specifications of APA300-FGG256

• Processor Series: APA300
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 290
• Data Ram Size: 73728
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 300 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Boundary Scan (JTAG)
ProASIC
1149.1, which defines a set of hardware architecture and
mechanisms for cost-effective, board-level testing. The
basic ProASIC
of the TAP (test access port), TAP controller, test data
registers, and instruction register
supports all mandatory IEEE 1149.1 instructions (EXTEST,
SAMPLE/PRELOAD and BYPASS) and the optional
IDCODE instruction
Each test section is accessed through the TAP, which has
five associated pins: TCK (test clock input), TDI and TDO
(test data input and output), TMS (test mode selector)
and TRST (test reset input). TMS, TDI and TRST are
equipped with pull-up resistors to ensure proper
operation when no input data is supplied to them. These
Figure 2-9 • ProASIC
Table 2-6 •
2 -8
EXTEST
SAMPLE/PRELOAD
IDCODE
ProASIC
PLUS
PLUS
Boundary-Scan Opcodes
devices are compatible with IEEE Standard
PLUS
Flash Family FPGAs
boundary-scan logic circuit is composed
PLUS
(Table
JTAG Boundary Scan Test Logic Circuit
2-6).
(Figure
Hex Opcode
I/O
I/O
2-9). This circuit
00
01
0F
I/O
I/O
v5.9
I/O
I/O
Bypass Register
pins are dedicated for boundary-scan test usage. Actel
recommends that a nominal 20 kΩ pull-up resistor is
added to TDO and TCK pins.
The TAP controller is a four-bit state machine (16 states)
that operates as shown in
1s and 0s represent the values that must be present at
TMS at a rising edge of TCK for the given state transition
to occur. IR and DR indicate that the instruction register
or the data register is operating in that state.
ProASIC
once for complete boundary-scan functionality to be
available. Prior to being programmed, EXTEST is not
available. If boundary-scan functionality is required prior
to programming, refer to online
Actel website and search for ProASIC
Table 2-6 •
CLAMP
BYPASS
I/O
Device
I/O
Logic
PLUS
Boundary-Scan Opcodes
devices have to be programmed at least
I/O
I/O
Test Data
Registers
Figure 2-10 on page
technical support
Hex Opcode
PLUS
BSDL.
05
FF
2-9. The
on the