LFXP3C-4TN100C Lattice, LFXP3C-4TN100C Datasheet - Page 272

• Manufacturer Part Number: LFXP3C-4TN100C
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 I/O 1.8/2.5/3.3V -4 Spd
• Manufacturer: Lattice

Specifications of LFXP3C-4TN100C

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
DCS MODE = NEG
At the falling edge (NEG) of SEL, the DCSOUT changes from CLK0 to CLK1.
DCS MODE = HIGH_LOW
SEL is active high (HIGH) to select CLK1, and the disabled output is LOW.
DCS MODE = LOW_LOW
SEL is active low (LOW) to select CLK0, and the disabled output is LOW.
DCS MODE = HIGH_HIGH
SEL is active high (HIGH) to select CLK1, and the disabled output is HIGH.
DCS MODE = LOW_HIGH
SEL is active low (LOW) to select CLK0, and the disabled output is HIGH.
DCSOUT
SEL
CLK1
DCSOUT
CLK1
SEL
CLK0
- Switch low at CLK1 falling edge.
- If SEL is low, output stays low at on
CLK1 rising edge. SEL must not
change during setup prior to rising clock.
DCS MODE = HIGH_LOW
SEL Falling edge:
- Wait for CLK1 falling edge,
- Switch output at CLK0 falling edge
latch output & remain low
DCS MODE = NEG
11-16
DCSOUT
sysCLOCK PLL Design and Usage Guide
SEL
CLK0
- Switch low at CLK0 falling edge.
- If SEL is high, output stays low at
on CLK0 rising edge.
SEL Rising edge:
- Wait for CLK0 falling edge,
- Switch output at CLK1 falling edge
DCS MODE = LOW_LOW
latch output & remain low
LatticeECP/EC and LatticeXP