LFXP3C-4TN144C Lattice, LFXP3C-4TN144C Datasheet - Page 267
LFXP3C-4TN144C
Manufacturer Part Number
LFXP3C-4TN144C
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V -4 Spd
Manufacturer
Lattice
Specifications of LFXP3C-4TN144C
Number Of Programmable I/os
100
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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LFXP3C-4TN144C
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Quantity:
135
Company:
Part Number:
LFXP3C-4TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Part Number:
LFXP3C-4TN144C-3I
Manufacturer:
TI
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19
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Lattice Semiconductor
From the loop:
Assume f
Equation (6) becomes:
From equation (1):
Clock Distribution in LatticeECP/EC and LatticeXP
The clock inputs are selected from external I/Os, the sysCLOCK PLLs or general routing. These clock inputs are
fed through the chip via a clock distribution system.
LatticeECP/EC and LatticeXP devices provide a quadrant-based primary and secondary clock structure.
Primary Clock Sources and Distribution
Each quadrant has four primary clock nets: CLK0, CLK1, CLK2 and CLK3. CLK2 and CLK3 provide dynamic clock
selection (DCS) capability. Figure 11-8 illustrates the block diagram of the primary clock distribution.
Figure 11-8. Primary Clocks and Center Switch Boxes
Note: Two PLLs are available in LatticeECP/EC/XP-6 or smaller devices.
PLL*
PLL
f
f
f
f
f
f
f
PCLKT7
INMAX
OUTKMIN
OUTKMAX
INMIN
INMAX
OUTMIN
OUTMAX
INMAX
CLKOP
CLKOS
CLKOK
CLKOP
CLKOS
CLKOK
= ((f
= f
= (f
= 420
= f
= f
PFDMAX
= f
= f
VCOMAX
VCOMIN
INMIN
INMAX
OUTMIN
OUTMAX
* (N/M), if below 25 * N round up to 25 * N
* M = 420 * M
* (N/M), if above 420 round down to 420
/ (V*N))*M, if below 25 * M round up to 25 * M
/ (V*N))*M, if above 420 round down to 420
/ K
/ K
General
Routing
General
Routing
QUADRANT TL
QUADRANT BL
CLK0
CLK0
16:1
16:1
PLL*: For LatticeECP/EC/XP-10 and larger devices
Primary Clocks in Center Switch Box
CLK1
CLK1
16:1
16:1
12:1 12:1 12:1 12:1
12:1 12:1 12:1 12:1
CLK2
CLK2
DCS
DCS
CLK3
CLK3
DCS
DCS
11-11
12:1 12:1 12:1 12:1
12:1 12:1 12:1 12:1
sysCLOCK PLL Design and Usage Guide
DCS
DCS
CLK3
CLK3
CLK2
CLK2
DCS
DCS
QUADRANT TR
QUADRANT BR
CLK1
CLK1
16:1
16:1
LatticeECP/EC and LatticeXP
(10)
(11)
(12)
(13)
(9)
CLK0
CLK0
16:1
16:1
General
Routing
General
Routing
CLKOP
CLKOS
CLKOK
CLKOP
CLKOS
CLKOK
PCLKT2
PLL*
PLL
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