LFXP3C-4TN144C Lattice, LFXP3C-4TN144C Datasheet - Page 146
LFXP3C-4TN144C
Manufacturer Part Number
LFXP3C-4TN144C
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V -4 Spd
Manufacturer
Lattice
Specifications of LFXP3C-4TN144C
Number Of Programmable I/os
100
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
The programmable drive feature also allows the user to match to the impedance of the transmission line.
Table 8-4 shows the drive current setting required to match 50¾ transmission line with 50¾ and 200¾ termina-
tions.
Table 8-4. Impedance Matching Using Programmable Drive Strength
The actual impedance matching may vary on the transmission line design and the load. To find the best matching,
it is recommended to drive the transmission line with different combinations of I/O standards and drive strengths
that best match the line impedance. Lattice provides IBIS buffer models for the users to further analyze the imped-
ance matching.
The figure below shows how this impedance matching is done for a 50¾ transmission line with 200¾ termination
using LVCMOS18 I/O buffers programmed to drive 16mA, 12mA, 8mA and 4mA. From this experiment it is empiri-
cal that the best matching is achieved with the 8mA drive setting.
Figure 8-2. Impedance Matching for a 50¾ Transmission Line with 200¾ Termination
50¾ Transmission
LVCMOS18 16mA
Line Termination
200
(¾)
50
I/O Standard
LVCMOS18
LVCMOS33
LVCMOS18
LVCMOS33
8-6
Drive Strength (mA)
LVCMOS18 12mA
12
16
20
LatticeECP/EC and LatticeXP
8
sysIO Usage Guide
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