A2F200M3F-1FGG484 Actel, A2F200M3F-1FGG484 Datasheet - Page 91

• Manufacturer Part Number: A2F200M3F-1FGG484
• Description: FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
• Manufacturer: Actel

Specifications of A2F200M3F-1FGG484

• Processor Series: A2F200
• Core: ARM Cortex M3
• Number Of Logic Blocks: 8
• Maximum Operating Frequency: 120 MHz
• Number Of Programmable I/os: 161
• Data Ram Size: 4608 bit
• Delay Time: 200 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 200000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-94 • ABPS Performance Specifications
Specification
Input voltage range (for driving ADC
over its full range)
Analog gain (from input pad to ADC
input)
Gain error
Input referred offset voltage
SINAD
Non-linearity
Effective number of bits (ENOB)
Large-signal bandwidth
ENOB
Analog Bipolar Prescaler (ABPS)
With the ABPS set to its high range setting (GDEC = 00), a hypothetical input voltage in the range –15.36
V to +15.36 V is scaled and offset by the ABPS input amplifier to match the ADC full range of 0 V to 2.56
V using a nominal gain of –0.08333 V/V. However, due to reliability considerations, the voltage applied to
the ABPS input should never be outside the range of –11.5 V to +14.4 V, restricting the usable ADC input
voltage to 2.238 V to 0.080 V and the corresponding 12-bit output codes to the range of 3581 to 128
(decimal), respectively.
Unless otherwise noted, ABPS performance is specified at 25°C with nominal power supply voltages,
with the output measured using the internal voltage reference with the internal ADC in 12-bit mode and
100 KHz sampling frequency, after trimming and digital compensation; and applies to all ranges.
=
SINAD 1.76 dB
-------------------------------------------- -
6.02 dB/bit
–
EQ 11
GDEC[1:0] = 11
GDEC[1:0] = 10
GDEC[1:0] = 01
GDEC[1:0]
maximum rating)
GDEC[1:0] = 11
GDEC[1:0] = 10
GDEC[1:0] = 01
GDEC[1:0] = 00
–40ºC to +100ºC
GDEC[1:0] = 11
GDEC[1:0] = 10
GDEC[1:0] = 01
GDEC[1:0] = 00
RMS deviation from BFSL
GDEC[1:0] = 11
(±2.56 range), –1 dBFS input
–1 dBFS input
12-bit mode 10 KHz
12-bit mode 100 KHz
10-bit mode 10 KHz
10-bit mode 100 KHz
8-bit mode 10 KHz
8-bit mode 100 KHz
–40ºC to +100ºC
–40ºC to +100ºC
–40ºC to +100ºC
–40ºC to +100ºC
Test Conditions
=
R e v i s i o n 6
00
(limited
SmartFusion Intelligent Mixed Signal FPGAs
by
–0.31
–1.00
–0.34
–0.90
–0.61
–1.05
–0.39
–1.06
Min.
–2.8
–2.8
8.6
8.6
8.5
8.5
7.7
7.7
53
See note 1
–0.0833
±10.24
–0.125
±2.56
±5.12
–0.25
–0.07
–0.07
–0.07
–0.07
Typ.
–0.5
–0.4
–0.4
9.1
9.1
8.9
8.9
7.8
7.8
56
1
Max.
0.31
0.34
0.35
0.35
1.47
1.37
1.35
1.38
0.7
0.7
0.5
Units
% FR
% FR
% FR
% FR
% FR
% FR
% FR
% FR
% FR
MHz
Bits
Bits
Bits
Bits
Bits
Bits
V/V
V/V
V/V
V/V
dB
%
%
V
V
V
V
2- 79